tag: Mentor

5G Verification Is Impossible Without Emulation
By Mentor, a Siemens Business - 23 Oct, 2019 - Comments: 0

Emulation, combined with a rich assortment of virtualized versions of the many protocols that 5G will require, is the only practical way of ensuring that the first round of silicon built will be the production version, able to handle all of the functions and configurations that it might be faced with and having the tight performance characteristics needed for successful integration into a 5G sy... » read more

Blog Review: Oct. 23
By Jesse Allen - 23 Oct, 2019 - Comments: 0

ANSYS' Magdy Abadir digs into the challenges associated with identifying and modeling electromagnetic crosstalk and the architectural and design trends that contribute to it. Cadence's Paul McLellan listens in as automotive security expert Charlie Miller points to how close we are to Level 4 autonomy and where in a car attack surfaces lie. Mentor's Brent Klingforth checks out the process ... » read more

Manufacturing Bits: Oct. 22
By Mark LaPedus - 22 Oct, 2019 - Comments: 0

3.5D chip packaging In a recent paper, PacTech has described a vertical laser assisted bonding process for use in developing advanced 3.5D chip packages. Laser assisted bonding (LAB) is an interconnection technology used in IC packaging. It uses a laser as a thermal energy, which in turn connects a die bump and a substrate pad, according to Amkor, which is the original developer of LAB tech... » read more

Extending Portable Stimulus
By Brian Bailey - 16 Oct, 2019 - Comments: 0

It has been a year since Accellera's Portable Test and Stimulus Specification became a standard. Semiconductor Engineering sat down to discuss the impact it has had, and the future direction of it, with Larry Melling, product management director for Cadence; Tom Fitzpatrick, strategic verification architect for Mentor, a Siemens Business; Tom Anderson, technical marketing consultant for OneSpin... » read more

Blog Review: Oct. 16
By Jesse Allen - 16 Oct, 2019 - Comments: 0

Arm's Greg Yeric dives into the challenges facing the semiconductor industry and potential solutions that could possibly have huge impacts toward the year 2030, from DNA self-assembly to new physics, in an adaptation of his wide-ranging Arm TechCon keynote. Cadence's Paul McLellan considers Google's recent quantum computing achievement, what quantum supremacy really means, and where it leave... » read more

Pushing Memory Harder
By Brian Bailey - 14 Oct, 2019 - Comments: 4

In an optimized system, no component is waiting for another component while there is useful work to be done. Unfortunately, this is not the case with the processor/memory interface. Put simply, memory cannot keep up. Accessing memory is slow, and it can consume a significant fraction of the power budget. And the general consensus is this problem is not going away anytime soon, despite effort... » read more

Week In Review: Design, Low Power
By Jesse Allen - 11 Oct, 2019 - Comments: 0

M&A Dialog Semiconductor will acquire Creative Chips for approximately $80 million cash, with contingent consideration of up to $23 million. The move will expand Dialog's Industrial IoT portfolio, adding Creative Chips' industrial Ethernet and other mixed-signal products for connecting large numbers of IIoT sensors to industrial networks. Based in Bingen, Germany, Creative Chips was founded in... » read more

Seeing Is Believing: Visualizing Full Coverage Closure In Low-Power Designs
By Madhur Bhargava - 10 Oct, 2019 - Comments: 0

By Madhur Bhargava and Durgesh Prasad Lowering the power consumption and leakage in SoCs and other electrical designs has become a paramount concern in recent years. The reasons for this are many and well understood. The structures and techniques we use to accomplish this have made verification of so called low-power designs more complex and difficult than it is for designs where power usage... » read more

Focus Shifts To Wasted Power
By Brian Bailey - 10 Oct, 2019 - Comments: 0

Mobile phones made the industry aware of power, but now the focus is shifting to the total energy needed to perform a task. Activity that is unnecessary to perform the intended task is wasted power, and reducing it requires some new methodologies and structural changes within development teams. There is a broadening awareness about power. "The companies doing SoCs for mobile lead the charge ... » read more

Using Emulators For Power/Performance Tradeoffs
By Ann Mutschler - 10 Oct, 2019 - Comments: 1

Emulation is becoming the tool of choice for power and performance tradeoffs, scaling to almost unlimited capacity for complex chips used in data centers, AI/ML systems and smart phones. While emulation has long been viewed as an important but expensive asset for chipmakers trying to verify and debug chips, it is now viewed as an essential component for design optimization and analysis much ... » read more

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