tag: Mentor

Debug Tools Are Improving
By Brian Bailey - 12 Aug, 2019 - Comments: 0

Semiconductor Engineering sat down to discuss debugging complex SoCs with Randy Fish, vice president of strategic accounts and partnerships for UltraSoC; Larry Melling, product management director for Cadence; Mark Olen, senior product marketing manager for Mentor, a Siemens Business; and Dominik Strasser, vice president of engineering for OneSpin Solutions. Part one can be found here. Part two... » read more

Writing Reusable UPF For RTL And Gate-Level Low Power Verification
By Durgesh Prasad - 08 Aug, 2019 - Comments: 0

By Durgesh Prasad, Jitesh Bansal and Madhur Bhargava The Unified Power Format (UPF) is used to specify the power intent of a design. Once written, the UPF file is applied at every stage of the design cycle — starting with the RTL, then the gate-level, and finally during place and route. A major problem is that the UPF needs to be refined or modified at every stage to keep it compatible ... » read more

Optimizing Power For Learning At The Edge
By Brian Bailey - 08 Aug, 2019 - Comments: 0

Learning on the edge is seen as one of the Holy Grails of machine learning, but today even the cloud is struggling to get computation done using reasonable amounts of power. Power is the great enabler—or limiter—of the technology, and the industry is beginning to respond. "Power is like an inverse pyramid problem," says Johannes Stahl, senior director of product marketing at Synopsys. "T... » read more

Determining Where Power Analysis Matters Most
By Ann Mutschler - 08 Aug, 2019 - Comments: 0

How much accuracy is required in every stage of power analysis is becoming a subject of debate, as engineering teams wrestle with a mix of new architectures, different use cases and increasing pressure to get designs out on time. The question isn't whether power is a critical factor in designs anymore. That is a given. It is now about the most efficient way to tackle those issues, as well as... » read more

Reusable UPF: Transitioning From RTL To Gate Level Verification
By Mentor, a Siemens Business - 07 Aug, 2019 - Comments: 0

This paper highlights the differences between an RTL UPF and a Gate Level Simulation UPF, and presents a new methodology to write RTL UPF in such a way that minimal changes are required during gate-level power verification. To read more, click here. » read more

Are Digital Twins Something For EDA To Pursue?
By Ann Mutschler - 07 Aug, 2019 - Comments: 0

‘Digital Twins’ are one of the new, fashionable key concepts for system developers, but do they fit with EDA? How many different types of engines do these twins run on – abstract simulation, signal-based RTL simulation, emulation, prototyping, actual silicon? What should the use models be called for digital twinning – like reproduction of bugs from silicon in emulation? Or optimizing th... » read more

Blog Review: Aug. 7
By Jesse Allen - 07 Aug, 2019 - Comments: 0

Synopsys' Taylor Armerding considers whether ransomware attacks on cities aren't only about money but if there are political motivations for intentionally sowing chaos and dysfunction. Cadence's Paul McLellan takes a look at the different way radio spectrum for 5G is being allocated in the U.S., which recently auctioned 24GHz bands for mmWave, and the rest of the world, which has focused on ... » read more

More Semiconductor Data Moving To Cloud
By Ed Sperling - 06 Aug, 2019 - Comments: 0

The cloud is booming. After years of steady growth it has begun to spike, creating new options for design, test, analytics and AI, all of which have an impact on every segment of the semiconductor industry. The initial idea behind the cloud is that it would supplement processing done on premises, adding extra processing power wherever necessary, such as in the verification and debug stages o... » read more

How Many Test Miles Make A Vehicle Safe?
By Kevin Fogarty - 06 Aug, 2019 - Comments: 0

The road to reliable safety testing of autonomous vehicles (AVs) is shifting left. Standards groups are beginning to publish functional safety standards that could make it possible to verify what a machine-learning AV pilot application will do in a traffic situation even before hardware or software is released from validation testing. This kind of approach has been possible for some time in ... » read more

Hierarchical DFT On A Flat Layout Design
By Vidya Neerkundar - 06 Aug, 2019 - Comments: 0

The use of hierarchical DFT methods is growing as design size and complexity stresses memory requirements and design schedules.  Hierarchical DFT divides the design into smaller pieces, creates test structures and patterns at the core level, then retargets the core patterns to the chip level. But, if you need to perform the physical place and route on the full flat design, can you still take a... » read more

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