tag: Mentor

Week In Review: Design, Low Power
By Jesse Allen - 26 Apr, 2019 - Comments: 0

A new working group has been proposed by Accellera to focus on the standardization of analog/mixed signal extensions (AMS) for the Universal Verification Methodology (UVM) standard. “Our ambition is to apply UVM for both digital and analog/mixed-signal verification,” said Martin Barnasconi, Accellera Technical Committee Chair. “The UVM-AMS PWG will assess the benefits of creating analog a... » read more

Moving Beyond Geometries: Context-Aware Verification Improves Design Quality And Reliability
By Sherif Hany - 25 Apr, 2019 - Comments: 0

Context-aware checks integrate physical and electrical information to evaluate a wide range of design conditions, from advanced design rule compliance, to circuit and reliability verification, to design optimization and finishing. Automated context-aware checking provides designers with actionable results that improve both debugging efficiency and verification precision. Introduction Many p... » read more

Automotive, AI Drive Big Changes In Test
By Ann Mutschler - 25 Apr, 2019 - Comments: 0

Design for test is becoming enormously more challenging at advanced nodes and in increasingly heterogeneous designs, where there may be dozens of different processing elements and memories. Historically, test was considered a necessary but rather mundane task. Much has changed over the past year or so. As systemic complexity rises, and as the role of ICs in safety-critical markets continues ... » read more

When Verification Leads
By Brian Bailey - 25 Apr, 2019 - Comments: 0

Semiconductor Engineering sat down to discuss the implications of having an executable specification that drives verification with Hagai Arbel, CEO for VTool; Adnan Hamid, CEO for Breker Verification; Mark Olen, product marketing manager for Mentor, a Siemens Business; Jim Hogan, managing partner of Vista Ventures; Sharon Rosenberg, senior solutions architect for Cadence Design Systems; and Tom... » read more

IC Design: Preparing For The Next Node
By Mentor, a Siemens Business - 25 Apr, 2019 - Comments: 0

The challenges of preparing for the next process node require constant preparation by the foundries, the EDA industry, and the design companies. Learn how Mentor works to prepare the Calibre nmPlatform for each “next node,” and ensure that its customers have the tools and performance they need to succeed. To read more, click here. » read more

The Case For Embedded FPGAs Strengthens And Widens
By Brian Bailey - 25 Apr, 2019 - Comments: 2

The embedded FPGA, an IP core integrated into an ASIC or SoC, is winning converts. System architects are starting to see the benefits of eFPGAs, which offer the flexibility of programmable logic without the cost of FPGAs. Programmable logic is especially appealing for accelerating machine learning applications that need frequent updates. An eFPGA can provide some architects the cover they ne... » read more

Blog Review: April 24
By Jesse Allen - 24 Apr, 2019 - Comments: 0

Rambus' Steven Woo checks out changes in the hardware used for neural network training and the importance of co-design of hardware and software. Cadence's Meera Collier makes an argument for why vehicle sensors watching the driver could prevent some distraction and fatigue-related crashes. Synopsys' Dan Lyon and Garrett Sipple point to some best practices for how to deal with a changing t... » read more

Week In Review: Design, Low Power
By Jesse Allen - 19 Apr, 2019 - Comments: 0

Intel acquired vision and video FPGA IP company Omnitek. Founded in 1998, the Basingstoke, England-based company has produced FPGA IP cores for video processing including conversion and enhancement, creating arbitrary image warps on a real time video stream, connectivity, and deep learning and AI inferencing. Terms of the deal were not disclosed. Qualcomm and Apple have dropped all litigatio... » read more

Designing For The Edge
By Ann Mutschler - 17 Apr, 2019 - Comments: 0

Chip and system architectures are beginning to change as the tech industry comes to grips with the need to process more data locally for latency, safety, and privacy/security reasons. The emergence of the intelligent edge is an effort to take raw data from endpoints, extract the data that requires immediate action, and forward other data to various local, regional or commercial clouds. The b... » read more

The Role Of EDA In AI
By Brian Bailey - 17 Apr, 2019 - Comments: 0

Semiconductor Engineering sat down to discuss the role that EDA has in automating artificial intelligence and machine learning with Doug Letcher, president and CEO of Metrics; Daniel Hansson, CEO of Verifyter; Harry Foster, chief scientist verification for Mentor, a Siemens Business; Larry Melling, product management director for Cadence; Manish Pandey, Synopsys fellow; and Raik Brinkmann, CEO ... » read more

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