tag: Mentor

The Week In Review: Design
By Jesse Allen - 02 Nov, 2018 - Comments: 0

M&A GlobalFoundries formed Avera Semiconductor, a wholly-owned subsidiary focused on custom ASIC designs. While Avera will use its relationship with GF for 14/12nm and more mature technologies, it has a foundry partnership lined up for 7nm. The new company's IP portfolio includes high-speed SerDes, high-performance embedded TCAMs, ARM cores and performance and density-optimized embedded SR... » read more

Automakers Gear Up For Autonomy
By Ann Mutschler - 01 Nov, 2018 - Comments: 0

Even though it’s going to be a number of years before autonomous cars are everywhere, the technology to make it happen is already rolling out in stages, giving the automotive ecosystem a chance to gear up as development happens. From electronic fleet management systems, which are already prevalent in semi trucks today, to more sophistication in passenger vehicle driver assistance features, it... » read more

Streamlining Public EV Charging
By Dirk Vogel - 01 Nov, 2018 - Comments: 0

It’s really quite simple. Do we, as a society, want to see more electric vehicles (EVs) on the road? What will it take for you to consider an EV? If widespread adoption is to occur, the one thing we must improve upon is the public EV recharging station. Up until now, EV charging at home has been a rather straight-forward process. The driver plugs the vehicle in during the evening hou... » read more

Connected Cars: From Chip To City
By Ann Mutschler - 01 Nov, 2018 - Comments: 0

As the automotive industry moves closer to autonomous vehicles, ecosystem players are focusing on the infrastructure pieces needed to make autonomous technology a reality for the first adopters, which are most likely commercial fleets. Vehicle-to-infrastructure (V2I or v2i) is a communications model that allows vehicles to share information with the components that support a country's hi... » read more

Layout Driven Design With L-Edit Photonics
By Mentor, a Siemens Business - 31 Oct, 2018 - Comments: 0

Advances in integrated circuit technology and fabrication have made it possible to leverage traditional CMOS fabrication processes and materials and apply them to the design of Photonic Integrated Circuits (PICs). The combination of PICs with traditional electronic integrated circuits, called integrated photonics, is the ability to move, modulate, and detect light on a single IC. While there is... » read more

Blog Review: Oct. 31
By Jesse Allen - 31 Oct, 2018 - Comments: 0

Mentor's Joe Hupcey III digs into handling memories effectively with formal through abstraction and the easiest ways to address memory-related inconclusive results. Cadence's Paul McLellan explains DARPA's CHIPS program that aims to lower semiconductor design costs through chiplet-based designs, the current status of the work, and what the next steps will be. Synopsys' Sangeeta Kulkarni c... » read more

The Impact of Domain Crossing on Safety
By Brian Bailey - 31 Oct, 2018 - Comments: 0

Semiconductor Engineering sat down to discuss problems associated with domain crossings with Alex Gnusin, design verification technologist for Aldec; Pete Hardee, director, product management for Cadence; Joe Hupcey, product manager and verification product technologist for Mentor, a Siemens Business; Sven Beyer, product manager design verification for OneSpin; and Godwin Maben, applications en... » read more

The Impact of Moore’s Law Ending
By Brian Bailey - 29 Oct, 2018 - Comments: 2

Over the past couple of process nodes the chip industry has come to grips with the fact that Moore's Law is slowing down or ending for many market segments. What isn't clear is what comes next, because even if chipmakers stay at older nodes they will face a series of new challenges that will drive up costs and increase design complexity. Chip design has faced a number of hurdles just to get ... » read more

Week In Review: Design, Low Power
By Jesse Allen - 26 Oct, 2018 - Comments: 0

Tools OneSpin launched a formal verification tool that integrates with all major simulators, coverage databases and viewers, and chip design verification planning tools to provide a comprehensive view of verification progress. Comprised of two new formal apps, it can identify unreachable coverage points and provide them to the simulator to reduce wasted effort. Synopsys released the latest ... » read more

The Race To Design Larger Systems
By Ed Sperling - 25 Oct, 2018 - Comments: 0

For more than a decade, tools vendors and design houses have been talking about leveraging their tools and expertise to help design systems of systems. They're finally getting their chance. The basic idea behind this strategy has always been that issues inside any electronic system—performance, power, signal integrity, area—have all been dealt all the way down to the sub-atomic level in ... » read more

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