tag: Mentor

Addressing The Complex Challenges In Low-Power Design And Verification
By Mentor, a Siemens Business - 09 Aug, 2017 - Comments: 0

This paper provides a comprehensive analysis of various complex debug problems faced in low-power design and verification. By using relevant examples it demonstrates how these issues can be either avoided or easily solved. We will also highlight some of the common pitfalls that low-power designers can avoid, which otherwise can lead to complex low-power issues that are difficult to debug at lat... » read more

Blog Review: Aug. 9
By Jesse Allen - 09 Aug, 2017 - Comments: 0

Cadence's Paul McLellan digs into a recently discovered vulnerability in the Broadcom Wi-Fi chip used in many smartphones and why it should be a wakeup call for SoC designers. Mentor's Craig Armenti considers whether work-in-process design data management is an asset or a liability. Synopsys' Thomas M. Tuerke notes that in code, as in medicine, proper hygiene is should be treated as a con... » read more

Advanced Packaging Moves To Cars
By Ann Mutschler - 07 Aug, 2017 - Comments: 0

By Ann Steffora Mutschler and Ed Sperling As automotive OEMs come up to speed on electrification of vehicles, each at their own pace, they are starting to embrace novel packaging approaches as a way to differentiate themselves in an increasingly competitive market. Wirebond used to dominate this market, where most of the chips were relatively unsophisticated and product cycles were slow�... » read more

Solving The Design And Verification Challenges Of High Density Advanced Packaging
By Mentor, a Siemens Business - 07 Aug, 2017 - Comments: 0

This paper discusses ways in which design teams can apply silicon (IC) type processes to the design and verification of the emerging HDAP packages. High Density Advanced Packaging, or HDAP, is the next-generation architecture for increased functional density, higher performance, lower power, smaller PCB footprints, and thinner profiles. This new “breed” of disruptive packaging technology... » read more

5 Big Under-The-Hood Engineering Challenges In Building Autonomous Vehicles
By Puneet Sinha - 03 Aug, 2017 - Comments: 0

Stories about autonomous vehicles are regular fare in the tech news cycle and usually include forecasts about the eventual ascendancy of self-driving cars. The Boston Consulting Group, for example, says that by 2035, 25% of all cars will have partial or full autonomy, with total global sales growing from near-zero levels in 2015 to $42 billion in 2025 and ~ $77 billion by 2035. In short few ye... » read more

Flexible Devices Drive New IoT Apps
By Jeff Dorsch - 03 Aug, 2017 - Comments: 1

Printed and flexible electronics are becoming almost synonymous with many emerging applications in the IoT, and as the technologies progress so do the markets that rely on those technologies. Flexible [getkc id="187" kc_name="sensors"] factor into a number of [getkc id="76" kc_name="IoT"] use cases such as agriculture, health care, and structural health monitoring. Other types of flexible de... » read more

Finally, A Painless Solution For Analog Verification Management
By Mentor, a Siemens Business - 03 Aug, 2017 - Comments: 0

Usually, teams manage analog simulations manually or they use complex and expensive tools that require intricate setup and proprietary test plans before they can be deployed. What teams need is an easy way to manage analog verification in order to track the large number of simulations for each project. Tracking simulation results at all levels for each team member and project managers requires ... » read more

Blog Review: Aug. 2
By Jesse Allen - 02 Aug, 2017 - Comments: 0

In a video, Cadence's Marc Greenberg describes the post-package repair capability in LPDDR4 and why it's important for future LP/DDR5 memories. Synopsys' Kiran Vittal looks at formal, machine learning, and when computers beat humans at games. Mentor's Matt Knowles digs into how cell-aware diagnosis works and why it can find tricky finFET defects. ARM's Freddi Jeffries digs into why com... » read more

The Week In Review: Design
By Jesse Allen - 28 Jul, 2017 - Comments: 0

IP Synopsys unveiled High Bandwidth Memory 2 (HBM2) IP. The package includes PHY, controller and verification IP and supports data rates up to 2400Mb/s, 20% faster than the JEDEC standard specification. The controller supports pseudo-channel operation in either lock step or memory interleaved mode, and the PHY offers four trained power management states and fast frequency switching. Cadence... » read more

Achieving Separation On Multiprocessor SoCs For Enhanced Safety And Security
By Dan Driscoll - 27 Jul, 2017 - Comments: 0

As I read my colleague Andrew Caples’ article on The Blurring of Safety and Security for Embedded Devices, I immediately started to think of the Xilinx UltraScale+ MPSoC – as I have engaged with numerous customers about using this chip for both safety and security purposes, and the requirements for both areas are definitely starting to blur. I quickly realized a blog about the Xilinx... » read more

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