tag: Mentor

Blog Review: Aug. 30
By Jesse Allen - 30 Aug, 2017 - Comments: 0

Cadence's Meera Collier explains machine learning, unsupervised algorithms, and why Facebook's recently publicized AI chatbot conversation isn't as inscrutable as it sounds. Synopsys' Robert Vamosi considers recently proposed legislation which seeks to mitigate the risk of botnets commandeering IoT devices used in the U.S. government, including limiting the use of hard-coded passwords and ce... » read more

Tools To Design CNNs
By Ann Mutschler - 28 Aug, 2017 - Comments: 2

Convolutional neural networks are becoming a mainstay in machine learning and artificial intelligence, allowing a network of distributed sensors to collect data and send them to a central brain for processing. This is a relatively simple idea in comparison to today's technology, and the idea of the [getkc id="261" kc_name="convolutional neural network"] has been around for some time. But bui... » read more

Collaborative Multi-Board System Design
By Craig Armenti - 24 Aug, 2017 - Comments: 0

Designing electronic systems has become measurably more complex during the past decade. Many of the products that are developed today are in-fact complex interconnected systems. Using the automotive market as an example, the first level of a system is an element; an individual component or sub-assembly that is designed to be part of a larger collaborating function. At the next level is the sub-... » read more

Portable Stimulus Status Report
By Brian Bailey - 24 Aug, 2017 - Comments: 0

The first release of the Portable Stimulus (PS) standard is slated for early next year. If it lives up to its promise, it could be the first new language and abstraction for verification in two decades. [getentity id="22028" e_name="Accellera"] uncorked the PS Early Adopter release at the Design Automation Conference (DAC) in June. The standard has been more than two years in the making by t... » read more

When Is Verification Complete?
By Ann Mutschler - 24 Aug, 2017 - Comments: 0

Deciding when verification is done is becoming a much more difficult decision, prompting verification teams to increasingly rely on metrics rather than just the tests listed in the verification plan. This trend has been underway for the past couple of process nodes, but it takes time to spot trends and determine whether they are real or just aberrations. The Wilson Research Group conducts a ... » read more

Blog Review: Aug. 23
By Jesse Allen - 23 Aug, 2017 - Comments: 0

Cadence's Madhavi Rao asks whether India should have more fabs and the role government policy should play. Synopsys' Kapil Rajpal checks out the Serial Peripheral Interface, which is emerging as a popular choice in automotive applications, and various vendor specific flavors. In a video, Mentor's Colin Walls explains inter-task communication and the basic mechanisms of how to pass data fr... » read more

Blog Review: Aug. 16
By Jesse Allen - 16 Aug, 2017 - Comments: 0

Cadence's Paul McLellan checks out how Imec sees the future of transistors and the challenges of 3D logic. Synopsys' Robert Vamosi gets a lesson on the electronic systems powering modern cars, and considers when it's ethical to hack one. Mentor's Colin Walls takes a look at how to pass data between RTOS tasks. Rambus' Aharon Etengoff looks at recent semi market predictions, from expand... » read more

How Reliable Are FinFETs?
By Ann Mutschler - 16 Aug, 2017 - Comments: 1

Stringent safety requirements in the automotive and industrial sectors are forcing chipmakers to re-examine a number of factors that can impact reliability over the lifespan of a device. Many of these concerns are not new. Electrical overstress (EOS), electrostatic discharge (ESD) and [getkc id="160" kc_name="electromigration"] (EM) are well understood, and have been addressed by EDA tools f... » read more

The Week In Review: Design
By Jesse Allen - 11 Aug, 2017 - Comments: 0

M&A Mentor acquired Valydate, provider of the VERA schematic integrity analysis tool. Founded in 2010, the Canadian company also offered signal and power integrity and static timing analysis services. Valydate's technology will be integrated with Mentor's Xpedition PCB design flow, though former Valydate CEO Michael Alam says it will continue to serve all EDA environments. Tools Aldec ... » read more

UPF Power Domains And Boundaries
By Progyna Khondkar - 10 Aug, 2017 - Comments: 0

The Universal Power Format (UPF) plays a central role in mitigating dynamic and static power in the battle for low-power in advanced process technology. A higher process node is definitely attractive as more functionality integration is possible in a smaller die area at a lower cost. However, in reality, this comes at the cost of exponentially increasing leakage power. This is because the minim... » read more

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