Antennas Everywhere


A simple rule when it comes to electronics is that while digital circuits scale, antennas do not. That may not sound like a serious problem until you consider that as more devices get connected—cars, watches, industrial equipment—and they add more features that require interaction with the outside world, they need more antennas to make it all work. In the future, there literally will be... » read more

NXP To Buy Freescale For $16.7B


By Ann Steffora Mutschler & Ed Sperling Dutch semiconductor giant NXP Semiconductors will buy Texas-based Freescale Semiconductor for $16.7 billion—$11.8 billion in cash, $5.6 billion worth of debts, minus $696 million in cash reserves—creating a combined company with a broad-based product portfolio and projected annual revenue of more than $10 billion. Given the size of the deal... » read more

Power And Noise Integrity For Analog / Mixed-Signal Designs


The convergence of advance process technology, increasing levels of integration, and higher operating frequencies pose considerable challenge to IP designers whose circuits are required to function in variety of conditions. Full-custom and mixed signal circuit designers ensure that their circuits will function by simulating for various operating conditions (PVT, input stimuli, etc). One key asp... » read more

The Week In Review: Design


Tools Mentor Graphics rolled out an extension to its PCB design platform that allows for synchronization of processes across multi-board systems. The new tool captures logic and system definitions for boards, cables, backplanes, cable assemblies, sensors and actuators. Cadence introduced a dynamic characterization solution for mixed signal blocks such as PLLs, data converters, high-speed tr... » read more

Extending Digital Verification Techniques For Mixed-Signal SoCs With VCS AMS


The growth in mixed-signal system-on-chip (SoC) designs is driven by many factors, including cost, performance and power consumption. This is fueled by many industry segments, including mobile communication, automotive, imaging, medical, networking and power management. The convergence of analog and digital blocks within the same die is driving the need for SoC design teams to adopt new verific... » read more

Design Rules Explode At New Nodes


Semiconductor Engineering sat down changing design rules with Sergey Shumarayev, senior director of custom IP design at Altera; Luigi Capodieci, R&D fellow at [getentity id="22819" comment="GlobalFoundries"]; Michael White, director of product marketing for Calibre Physical Verification at [getentity id="22017" e_name="Mentor Graphics"], and Coby Zelnik, CEO of [getentity id="22478" e_name=... » read more

Optimizing Analog For Power At Advanced Nodes


As any engineering manager will tell you, analog and digital engineers seem like they could be from different planets. While this has changed somewhat over time, [getkc id="52" comment="analog"] is still something of a mystery to many in [getkc id="81" kc_name="SoC"] design teams. Throw power management into the mix and things really get interesting. Improvements in analog/mixed-signal tools... » read more

Verification Planning And Requirement Tracking For Analog Design


Verifying designs to meet all specifications across all process corners has become an intractable problem from the perspective of debugging, managing, tracking, and meeting verification goals. Implementing a CDV methodology for analog designs can evolve analog design and verification to a standard process-based method that can be tracked and its progress measured. This paper aims to extend comm... » read more

IoT Brings Low Power To Forefront


Low power has become a primary design consideration over the past decade, driven by consumer portable devices packing in greater amounts of processing power and sophisticated communications, while at the same time providing extended battery life even though developments in battery technology have advanced little in the same timeframe. But the [getkc id="76" comment="Internet of Things"] (IoT) w... » read more

A Novel Approach To Dummy Fill For Analog Designs


With small geometry silicon processes, additional nonfunctional geometric structures are required to maintain layer planarity during the chemical/mechanical polishing (CMP) phase of processing. The automated layout flows to generate such geometries tend to be designed primarily for large system on chip (SOC) digital designs. When applied to mixed-signal layouts, these flows have been seen to ha... » read more

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