Boosting Production Performance: Ensuring Only Known-Good Sockets Enter Your Line


Efficient, stable, and high-yield semiconductor production depends on one often-overlooked factor: the health of your test sockets. In many factories, socket maintenance and inspection practices haven't kept pace with the demands of today’s high-density, high-speed packages. The result? Hidden marginal pins, unexpected downtime, multisite yield variation, and inflated manufacturing costs. ... » read more

Chip Industry Week In Review


China's Hefei Lumiverse Technology reportedly has developed a desktop-sized High Harmonic Generation light source that generates wavelengths as small as 1nm. One customer already has used it to produce 14nm chips, which was the original target node for EUV, according to one report. As a point of comparison, TSMC and Samsung didn't start using EUV until the 7nm node, relying instead on immersion... » read more

Beyond The Bottleneck: 3 Breakthroughs In High-Throughput Connector Testing


By Reagan Oliver and Jesse Ko Ensuring the quality of mass-produced electronic connectors without creating a production bottleneck remains a persistent challenge in manufacturing. As demand for speed and reliability increases, innovative testing solutions are emerging to meet this need head-on. This article breaks down three key breakthroughs in modern connector testing technology based on a... » read more

AI In Test Analytics: Promise Vs. Reality


The semiconductor industry is increasingly turning to artificial intelligence as the solution for increasing complexity in test analytics, hoping algorithms can tame the growing flood of production data. The need to extract actionable insight from that torrent is pressing. AI/ML (AI) models promise to find correlations buried in multidimensional datasets, predict failures before they occur, and... » read more

Enhancing Test Socket Performance Through Application-Specific Validation And System-Level Per-Pin OQC


As semiconductor devices continue to advance, the demand for reliable, high-performance test sockets has never been greater. Yet, traditional socket design validation methods—such as per-pin characterization and generic housing evaluations—often fall short of reflecting true application specific system-level performance. This gap between lab measurements and real-world application not only ... » read more

Metrology’s Growing Role In Reducing False Defects


When a good die fails test and gets scrapped, often no one notices, because false failures look identical to real ones. Yet across the industry, these phantom defects are quietly eroding yield, inflating test costs, and masking the true health of manufacturing processes. At advanced nodes and in heterogeneous packaging, where margins are already razor-thin, even minor variations in contact r... » read more

Case Study: Production Yield And Throughput Improvement Using The Known Good Socket Analysis


The test sockets, which are crucial components that directly interface with semiconductor IC packages, have a profound impact on device testing performance. Pins with high CRES not only cause false failures in the test but also lower bin grading results, which in turn increase the manufacturing cost due to reduced production performance. The ever-increasing demand driven by high-performance com... » read more

The Hidden Cost Of Contact Resistance


Contact resistance, or CRES, is one of those problems that most engineers prefer not to think about until it's staring them in the face. For years, it could be managed quietly with routine probe card cleaning or a scheduled socket swap. That approach worked well enough when pin counts were lower and devices pulled less current, but the ground has shifted since then. Today’s AI processors m... » read more

Advanced Electrical Test Capability For Better Defect Signature Detection In Advanced Package Development


As the semiconductor world excitingly explores the potential of new advanced package solutions for their intricate and novel designs, challenges arise from undetected defects caused by the complexity of the designs and the lack of accessibility to the interconnects for testing. This typically results in a long cycle time to achieve yield entitlement. Undetected defects at the development stage ... » read more

Metrology Under Pressure: Detecting Defects in Fine-Pitch Hybrid Bonding


As advanced packaging pushes deeper into the sub-10µm realm, traditional inspection and metrology systems are being forced to evolve with it. Hybrid bonding, a critical enabler of vertical integration and 3D system performance, relies on exceptionally tight alignment and defect-free bonding surfaces. But as interconnect pitch shrinks, even nanometer-scale variations in height, tilt, or cont... » read more

← Older posts Newer posts →