GPU Microarchitecture Integrating Dedicated Matrix Units At The Cluster Level (UC Berkeley)


A new technical paper titled "Virgo: Cluster-level Matrix Unit Integration in GPUs for Scalability and Energy Efficiency" was published by UC Berkeley. Abstract "Modern GPUs incorporate specialized matrix units such as Tensor Cores to accelerate GEMM operations central to deep learning workloads. However, existing matrix unit designs are tightly coupled to the SIMT core, limiting the size a... » read more

Characterizing Three Supercomputers: Multi-GPU Interconnect Performance


A new technical paper titled "Exploring GPU-to-GPU Communication: Insights into Supercomputer Interconnects" was published by researchers at Sapienza University of Rome, University of Trento, Vrije Universiteit Amsterdam, ETH Zurich, CINECA, University of Antwerp, IBM Research Europe, HPE Cray, and NVIDIA. Abstract "Multi-GPU nodes are increasingly common in the rapidly evolving landscape... » read more

Chip Industry Week In Review


The U.S. Department of Commerce and Texas Instruments (TI) signed a non-binding preliminary memorandum of terms to provide up to $1.6 billion in CHIPS Act funding towards TI’s investment of over $18 billion for three 300mm semiconductor wafer fabs under construction in Texas and Utah. TI also expects to get about $6 billion to $8 billion from the U.S. Department of Treasury’s Investmen... » read more

Building Smarter, Better Fabs


Battling labor shortages, faster ramp rates, and data overload, the process of designing and building greenfield fabs requires a combination of tech tools, failing earlier approaches and superior planning from day one. The complexity and scale of semiconductor fabs is skyrocketing as is the capital cost. Chipmakers are looking to ramp multibillion dollar fabs faster despite the hurdles of la... » read more

Chip Industry Technical Paper Roundup: August 13


New technical papers recently added to Semiconductor Engineering’s library: [table id=249 /] More ReadingTechnical Paper Library home   » read more

Analog Consolidation Spurs New Round Of Startups


A new wave of startups is rising to meet the growing need for specialized analog customization in chip design projects, opening the door to more affordable custom designs. These startups are breathing new life into a sector, which as a result of consolidation has favored only the largest chipmakers. As larger analog companies acquire smaller ones, many companies that were previously engaged ... » read more

Power Delivery Challenged By Data Center Architectures


Processor and data center architectures are changing in response to the higher voltage needs of servers running AI and large language models (LLMs). At one time, servers drew a few hundred watts for operation. But over the past few decades that has changed drastically due to a massive increase in the amount of data that needs to be processed and user demands to do it more quickly. NVIDIA's G... » read more

Secure Low-Cost In-DRAM Trackers For Mitigating Rowhammer (Georgia Tech, Google, Nvidia)


A new technical paper titled "MINT: Securely Mitigating Rowhammer with a Minimalist In-DRAM Tracker" was published by researchers at Georgia Tech, Google, and Nvidia. Abstract "This paper investigates secure low-cost in-DRAM trackers for mitigating Rowhammer (RH). In-DRAM solutions have the advantage that they can solve the RH problem within the DRAM chip, without relying on other parts of ... » read more

Chip Industry Week In Review


The U.S. Department of Commerce and Amkor Technology signed a deal to provide up to $400 million in funding, under the CHIPS and Science Act, to build a previously announced end-to-end advanced packaging plant. The combined funding is expected to total about $2 billion. The new facility will add some 2,000 jobs in Peoria, Arizona. The SK hynix Board approved its Yongin Semiconductor Cluster... » read more

Capturing Knowledge Within LLMs


At DAC this year, there was a lot of talk about AI and the impact it is likely to have. While EDA companies have been using it for optimization and improving iteration loops within the flow, the end users have been concentrating on how to use it to improve the user interface between engineers and tools. The feedback is very positive. Large language models (LLMs) have been trained on a huge a... » read more

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