New Standards Push Co-Packaged Optics

By Karen Heyman - 26 Apr, 2023 - Comments: 0

Co-packaged optics (CPOs) promise five times the bandwidth of pluggable connections, but the new architecture requires multiple changes to accommodate different applications. The Optical Internetworking Forum (OIF) recently published standards for co-packaged optics, which are the photonic industry’s hope for handling today’s faster Ethernet interfaces, as well as increasing speeds and p... » read more

High-Speed Signaling Drill-Down

By Bryon Moyer - 17 Jun, 2020 - Comments: 0

Chip interconnect standards have received a lot of attention lately, with parallel versions proliferating for chiplets and serial versions moving to higher speeds. The lowliest characteristic of these interconnect schemes is the physical signaling format. Having been static at NRZ (non-return-to-zero) for decades, change is underway. “Multiple approaches are likely to emerge,” said Brig ... » read more

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tag: Optical Interconnect Forum

New Standards Push Co-Packaged Optics

High-Speed Signaling Drill-Down

Trending Articles

Shift Left Is The Tip Of The Iceberg

NAND Flash Targets 1,000 Layers

One Chip Vs. Many Chiplets

FOPLP Gains Traction in Advanced Semiconductor Packaging

HBM Options Increase As AI Demand Soars

Knowledge Centers Entities, people and technologies explored

Related Articles

Shift Left Is The Tip Of The Iceberg

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NAND Flash Targets 1,000 Layers

3.5D: The Great Compromise

AI’s Role In Chip Design Widens, Drawing In New Startups

What Comes After HBM For Chiplets

Memory Fundamentals For Engineers

New AI Processors Architectures Balance Speed With Efficiency

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