The Week In Review: Design


Tools Mentor unveiled new formal-based technologies in the Questa Verification Solution. It offers formal-based RTL-to-RTL equivalence checking flows optimized for verification of manual low-power clock gating, bug fix and ECO validation, and ISO 26262 safety mechanism verification, which the company says which can reduce verification turnaround time by 10X. The app also offers expanded cloc... » read more

Blog Review: April 19


Mentor's Tom Fitzpatrick explains what the Portable Stimulus standard will do, what it won't, and why the choice of input language defined by the standard matters. Cadence's Paul McLellan listens in as IRDS chairman Paolo Gargini explains how long it takes technology breakthroughs to make out of the lab and into high-volume manufacturing. Synopsys' Robert Vamosi points to the recent sound... » read more

Understanding SerDes Signal Integrity Challenges


Signal integrity (SI) can perhaps best be defined as a set of measures of the quality of electrical signals, which are subject to the effects of noise, distortion and loss. Additional signal integrity issues include jitter, ringing, crosstalk, ground bounce and power supply noise. There are multiple factors that can negatively influence signal integrity, thereby causing errors and system fai... » read more

SerDes Signal Integrity Challenges At 28Gbps And Beyond


After nearly fifty years, NRZ technology continues to pose significant challenges as data rates approach 56Gbps and refreshed standards mandate increased receiver sensitivity (down to 35 mV). With shorter unit intervals and closing eyes, triggering becomes ever more complex and requires enhanced receiver equalization such as continuous-time-linear equalization and decision feedback equalization... » read more

Blog Review: April 12


Cadence's Paul McLellan discusses the legal concerns around autonomous vehicles, emotion-based driver monitoring, and the role of LiDAR, from the CASPA Symposium on Autonomous Driving. The IEEE Design & Test's Magdy Abadir interviews Mentor's Wally Rhines in a discussion ranging from EDA growth and its economics to the increasing complexity of verification. Synopsys' Robert Vamosi exa... » read more

Security: Losses Outpace Gains


Paul Kocher, chief scientist in [getentity id="22671" e_name="Rambus'"] Cryptography Research Division, sat down with Semiconductor Engineering to discuss the new threats to security, artificial intelligence and machine learning, and how to engineer a secure system. What follows are excerpts of that conversation. SE: Where are we with security? It seems that rather than getting better, thing... » read more

The Evolution Of Side-Channel Attacks


A side-channel attack can perhaps best be defined as any attack based on information gained from the physical implementation of a cryptosystem, rather than brute force or theoretical weaknesses in the algorithms. Put simply, all physical electronic systems routinely leak information about their internal process of computing via their power consumption or electromagnetic emanations. This mean... » read more

Ensuring Privacy in Next Generation Room Occupancy Sensing


For buildings and homes to become ‘smarter’ and more adaptive, new sensing technology must be capable of detecting, counting and tracking occupants regardless of motion. While next-generation sensor technology offers a glimpse of an exciting future in which buildings adapt and learn, real-world privacy issues will almost certainly have to be addressed before mainstream adoption is achieved.... » read more

Blog Review: April 5


In a video, Cadence's Megha Daga digs into the different architectural layers present in convolutional neural networks and how they contribute to object detection and classification in a real world scenario. Mentor's Mike Santarini argues that as things become increasingly connected, the stakes of bad design and bad verification are higher than they've ever been. Synopsys' Robert Vamosi w... » read more

HBM Upstages DDR In Bandwidth, Power


For graphics, networking, and high performance computing, the latest iteration of high-bandwidth memory (HBM) continues to rise up as a viable contender against conventional DDR, GDDR designs, and other advanced memory architectures such as the Hybrid Memory Cube. [getkc id="276" kc_name="HBM"] enables lower power consumption per I/O and higher bandwidth memory access with a more condensed f... » read more

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