tag: Si2

Defining The Next Standard Cell
By The SE Staff - 22 Jan, 2014 - Comments: 1

Synopsys, Intel and IBM all contributed technology to Si2 to create a standard version of parameterized cells, or PCells, for mixed-signal designs. The move is an attempt to smooth out design incompatibilities using Synopsys and Cadence technology. Cadence is the clear market leader in this space. But as more technology is developed using different vendors'  tools for integration in complex... » read more

Experts At The Table: What’s Next?
By Ed Sperling - 20 Jan, 2014 - Comments: 0

Semiconductor Engineering sat down with Sumit DasGupta, Si2; Simon Bloch, Samsung; Jim Hogan, long-time industry venture capitalist; Mike Gianfagna, vice president of marketing at eSilicon (VP of corporate marketing at Atrenta when this roundtable was held). What follows are excerpts of that discussion. SE: What’s going to really drive interest in low-power technology? Hogan: The world ... » read more

The Week In Review: System-Level Design
By Ed Sperling - 10 Jan, 2014 - Comments: 0

Cadence won a deal with Fraunhofer, which licensed its MPEG codecs for Tensilica HiFi DSP. (Cadence acquired Tensilica last year.) The AAC codecs combine speech and general-purpose audio into a unified system, which simplifies design because it works at any bit rate. Sonics won a deal with MediaTek, which licensed its NoC technology for an upcoming line of SoCs. MediaTek, based in Taiwan, is... » read more

Experts At The Table: What’s Next?
By Ed Sperling - 06 Jan, 2014 - Comments: 1

Semiconductor Engineering sat down with Sumit DasGupta, Si2; Simon Bloch, Samsung; Jim Hogan; Mike Gianfagna, vice president of marketing at eSilicon (VP of corporate marketing at Atrenta when this roundtable was held). What follows are excerpts of that discussion. SE: The future of technology isn’t just about technology. It’s about people and regulations, as well. Where are the hurdles ... » read more

Where Is 2.5D?
By Ed Sperling - 19 Dec, 2013 - Comments: 3

After nearly five years of concentrated research, development, test chips and characterization, 2.5D remains a possibility for many companies but a reality for very few. So what’s taking so long and why hasn’t all of this hype turned into production runs instead of test chips? Semiconductor Engineering spent the past two months interviewing dozens of people on this subject, from chipmakers ... » read more

Wanted: Standard Design Constraints
By Steve Schulz - 19 Dec, 2013 - Comments: 0

Lately, there has been increasing discussion in the industry about the need for a set of standards that specifically support an interoperable description of intent for analog and custom design, a.k.a. “analog design intent” standards. The driving need for such standardization is to enable far greater exchange of analog intent, with greater formalism and clarity, to greatly improve time-to-... » read more

Is There Light At The End Of Moore’s Tunnel?
By Brian Bailey - 18 Dec, 2013 - Comments: 2

Last month’s article, “Is There Light At The End Of Moore’s Tunnel,” examined the state of the industry in terms of integrating photonics components onto silicon. It concentrated on the piece that has been the hardest to achieve – the laser. However, as realizing that integration goal has become closer to reality, it has also waned in terms of the number of people who believe it is th... » read more

The Week In Review: System-Level Design
By Ed Sperling - 27 Nov, 2013 - Comments: 0

Synopsys won a deal with Germany’s Hyperstone, which will use Synopsys verification tools for SoCs in industrial, automotive and medical applications. As SoCs used in industrial and “safety-critical” markets grow in complexity and move to more advanced process nodes, more advanced tools also are necessary. Si2 uncorked a new release of its OpenAccess scripting interface—oaScript Exte... » read more

Is There Light At The End Of Moore’s Tunnel
By Brian Bailey - 22 Nov, 2013 - Comments: 2

Electrons are slow, clumsy and quite easily distracted. They’re slow because it now takes a signal longer to cross a chip than the period of the clock signal. They often don’t travel in straight lines as they collide with other atoms. And electromagnetic interference between adjacent signals can mess with the information they are transferring. On the other hand, light has none of these p... » read more

Experts At The Table: What’s Next?
By Ed Sperling - 21 Nov, 2013 - Comments: 1

Semiconductor Engineering sat down with Jim Hogan, long-time industry venture capitalist; Simon Bloch, senior director at Samsung Electronics; Sumit DasGupta, formerly Si2 senior vice president of engineering; and Mike Gianfagna, vice president of marketing at eSilicon (VP of corporate marketing at Atrenta when this roundtable was held). What follows are excerpts of that discussion. SE: What... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2026 SMG   |  Terms of Service  |  Privacy Policy