tag: Siemens EDA

Blog Review: Mar. 6
By Jesse Allen - 06 Mar, 2019 - Comments: 0

Synopsys' Snigdha Dua traces the evolution of memory from SDRAM to DDR5 and the techniques that provide each generation's speed increase. Cadence's Paul McLellan digs into the challenges of 112Gbps SerDes, including what makes PAM4 signaling different from NRZ and what goes into equalization and modeling. Mentor's Rich Edelman provides a quick tutorial on how to set up a custom UVM report... » read more

The Challenge Of RISC-V Compliance
By Brian Bailey - 28 Feb, 2019 - Comments: 0

The open-source RISC-V instruction set architecture (ISA) continues to gain momentum, but the flexibility of RISC-V creates a problem—how do you know if a RISC-V implementation fits basic standards and can play well with other implementations so they all can run the same ecosystem? In addition, how do you ensure that ecosystem development works for all implementations and that all cores that ... » read more

Can Debug Be Tamed?
By Brian Bailey - 28 Feb, 2019 - Comments: 0

Debug consumes more time than any other aspect of the chip design and verification process, and it adds uncertainty and risk to semiconductor development because there are always lingering questions about whether enough bugs were caught in the allotted amount of time. Recent figures suggest that the problem is getting worse, too, as complexity and demand for reliability continue to rise. The... » read more

Partitioning Drives Architectural Considerations
By Ann Mutschler - 25 Feb, 2019 - Comments: 0

Semiconductor Engineering sat down to explore partitioning with Raymond Nijssen, vice president of system engineering at Achronix; Andy Ladd, CEO at Baum; Dave Kelf, chief marketing officer at Breker; Rod Metcalfe, product management group director in the Digital & Signoff Group at Cadence; Mark Olen, product marketing group manager at Mentor, a Siemens Business; Tom Anderson, technical mar... » read more

Week In Review: Design, Low Power
By SE Staff - 15 Feb, 2019 - Comments: 0

Tools & IP Engineering simulation company ANSYS says thanks to new features in its ANSYS Twin Builder, product developers may be able save money in warranty and operational costs. The Twin Builder creates a digital twin of a systems in the field, enabling a convenient way to monitor and maintain systems remotely. The latest release adds predictive maintenance features for digital-twin runt... » read more

Gearing Up For 5G
By Brian Bailey - 14 Feb, 2019 - Comments: 0

5G has been touted as the new enabler for many market segments, including mobile phones, automotive, virtual reality, and IoT. But there are many questions and much speculation about when and how this new wireless standard will impact different market segments and what effect it will have on semiconductor design. With a promise of orders of magnitude improvement in communication speed an... » read more

MEMS & Sensors Technical Congress Focuses on Automotive, Emerging MEMS
By Heidi Hoffman - 08 Feb, 2019 - Comments: 0

This year’s MEMS & Sensors Technical Congress (MSTC), February 19-20, 2019, features a deep dive into the changing automotive sensor landscape, a look at emerging MEMS technologies, and an exploration of integration standards. The more technically focused of SEMI’s annual MEMS events, MSTC returns to Monterey, California, in conjunction with FLEX, the conference that highlights new form... » read more

Pushing AI Into The Mainstream
By Brian Bailey - 31 Jan, 2019 - Comments: 0

Artificial intelligence is emerging as the driving force behind many advancements in technology, even though the industry has merely scratched the surface of what may be possible. But how deeply AI penetrates different market segments and technologies, and how quickly it pushes into the mainstream, depend on a variety of issues that still must be resolved. In addition to a plethora of techni... » read more

Taming Concurrency
By Brian Bailey - 17 Jan, 2019 - Comments: 2

Concurrency adds complexity for which the industry lacks appropriate tools, and the problem has grown to the point where errors can creep into designs with no easy or consistent way to detect them. In the past, when chips were essentially a single pipeline, this wasn't a problem. In fact, the early pioneers of EDA created a suitable language to describe and contain the necessary concurrency ... » read more

Mostly Upbeat Outlook For Chips
By Brian Bailey - 17 Jan, 2019 - Comments: 1

2019 has started with cautious optimism for the semiconductor industry, despite dark clouds that dot the horizon. Market segments such as cryptocurrencies and virtual reality are not living up to expectations, the market for smart phones appears to be saturated, and DRAM prices are dropping, leading to cut-backs in capital expenditures. EDA companies are talking about sales to China being pu... » read more

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