tag: Siemens EDA

Beyond UVM Registers — Better, Faster, Smarter
By Mentor, a Siemens Business - 27 Jan, 2016 - Comments: 0

Adoption of SystemVerilog UVM is growing stronger. Verification teams are expanding their knowledge with respect to UVM features and capabilities. These verification teams are using the UVM Register layer with good success. But the UVM Register layer has many moving parts and intricate details. It can be difficult to adopt and it can be difficult to model complex registers. It is a complex syst... » read more

Debug: Last Bastion Of Automation
By Brian Bailey - 27 Jan, 2016 - Comments: 0

There have been a number of times when anecdotal evidence became folk law and then over time, the effort was put in to find out whether there was any truth in it. Perhaps the most famous case is the statement that verification consumes 70% of development time and resources. For years this “fact” was used in almost every verification presentation and yet nobody knew where the number had come... » read more

Blog Review: Jan. 27
By Jesse Allen - 27 Jan, 2016 - Comments: 0

There's an ocean of possibilities for transistors and interconnects at the 5nm node, says Cadence's Paul McLellan – but will any of them be feasible in time? How would you design R2-D2? Mentor's Joe Hupcey III lays out what low power techniques he thinks the Star Wars droid might require. It's not all clear skies in the world of FinFETs, as Synopsys' Graham Etchells continues his series... » read more

5nm Fab Challenges
By Mark LaPedus - 21 Jan, 2016 - Comments: 2

At a recent event, Intel presented a paper that generated sparks and fueled speculation regarding the future direction of the leading-edge IC industry. The company described a next-generation transistor called the nanowire FET, which is a finFET turned on its side with a gate wrapped around it. Intel’s nanowire FET, sometimes called a gate-all-around FET, is said to meet the device require... » read more

Automated Power Model Verification For Analog IPs
By Sierene Aymen - 21 Jan, 2016 - Comments: 0

By Sierene Aymen and Hartmut Marquardt Creating macro power models for analog intellectual property (IP) blocks is essential to enable the chip assembly group to effectively integrate these blocks within their place and route environment. These macro models, which define power domains, identify IP ports as signal, power, ground, or trivial ports, and describe the associations of signal pins ... » read more

Predictions For 2016: Semiconductors, Manufacturing And Design
By Brian Bailey - 21 Jan, 2016 - Comments: 0

Seventeen companies sent in their predictions for this year with some of them sending predictions from several people. This is in addition to the CEO predictions that were recently published. That is a fine crop of views for the coming year, especially since they know that they will be held accountable for their views and this year, just like the last, they will have to answer for them. We beli... » read more

Tech Talk: Double-Triple Patterning
By Brian Bailey - 21 Jan, 2016 - Comments: 0

Mentor Graphics' David Abercrombie shows the differences and challenges in double patterning versus triple patterning. [youtube vid= e0wZmjBbEf0] » read more

The Future of Package Design Verification: Assembly Design Kits
By Mentor, a Siemens Business - 20 Jan, 2016 - Comments: 0

Chip design companies and package assembly houses have no unified signoff verification process to ensure that an IC package meets manufacturability and performance requirements. Packages need a process that confirms the disparate products they contain can be manufactured within a single package. Mentor Graphics collaborated with Qualcomm and STATS ChipPAC to develop a prototype assembly design ... » read more

Blog Review: Jan. 20
By Jesse Allen - 20 Jan, 2016 - Comments: 0

How far can you go on solar power? 493 million miles, at least if you're the Juno spacecraft. Plus, winemaking gets a boost from submarine technology, in this week's top tech picks from Ansys' Bill Vandermark. Mentor's Steve Pateras digs into how automotive ICs bring a whole new set of requirements that are driving the evolution of memory BIST. If you're interested in neural networks and ... » read more

Will 5nm Happen?
By Mark LaPedus - 20 Jan, 2016 - Comments: 7

Chipmakers are ramping up their 16/14nm finFET processes, with 10nm finFETs expected to ship sometime in late 2016 or early 2017. So what’s next? The foundries can see a path to extend the finFET transistor to 7nm, but the next node, 5nm, is far from certain and may never happen. Indeed, there are several technical and economic challenges at 5nm. And even if 5nm happens, only a few compani... » read more

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