tag: Siemens EDA

The New Face of Formal
By Brian Bailey - 04 Nov, 2015 - Comments: 0

Semiconductor engineering sat down to discuss the recent growth in adoption of formal technologies and tools with Lawrence Loh, product engineering group director at [getentity id="22032" e_name="Cadence"], Praveen Tiwari, senior manager R&D, verification group at [getentity id="22035" e_name="Synopsys"], Harry Foster, chief scientist at [getentity id="22017" e_name="Mentor Graphics"], Normando... » read more

Making IP Secure
By Ann Mutschler - 02 Nov, 2015 - Comments: 0

[getkc id="43" comment="IP"] security is coming under increasing scrutiny as concerns about system and hardware security escalate. For IP, this is particularly critical because commercially available IP touches many players in the semiconductor and software ecosystem. IP users want to ensure they are using the IP as the provider intended and that they are protected against malicious code. IP... » read more

The Week In Review: Design/IoT
By Jesse Allen - 30 Oct, 2015 - Comments: 0

Tools Aldec introduced Hybrid Emulation including support for ARM Fast Models. Aldec says the capability to link an SoC emulation hardware platform with a virtual platform allows both software and hardware teams to work on the most up-to-date version of the project, long before first silicon is available, or even much of the RTL or IP has been completed. eSilicon's online quoting tools fo... » read more

HW Vs. SW: Who’s Leading Whom?
By Brian Bailey - 29 Oct, 2015 - Comments: 6

In the past, technologies were developed in the software world that have languished until they were taken up by the hardware community. Then they were refined and polished and became fully integrated into the hardware development and verification flow. Examples are lint and formal. That was followed by attempts to migrate methodologies, such as object-oriented programming, which is the basis fo... » read more

Hybrid Emulation Gets More Hybrid
By Ed Sperling - 29 Oct, 2015 - Comments: 0

Rising chip complexity is creating a booming emulation business, as chipmakers working at advanced nodes turn to bigger iron to get chips out the door on time. What started as a "shift lift"—doing more things earlier in the design cycle—is evolving into a more complex mix of hardware-accelerated verification for both hardware and software. There are even some new forays into power explor... » read more

Culture Clash In Analog
By Ann Mutschler - 29 Oct, 2015 - Comments: 2

The analog/mixed signal world is being shaken up by a mix of new tools, an influx of younger engineers with new and broader approaches, and an emphasis on changing methodologies to improve time to market. Analog and digital engineers have never quite seen eye-to-eye. Analog teams leverage techniques that have been around, in some cases, for decades, while digital teams rely heavily on the la... » read more

The New Face Of Formal
By Brian Bailey - 29 Oct, 2015 - Comments: 0

Semiconductor Engineering sat down to discuss the recent growth in adoption of formal technologies and tools with Lawrence Loh, product engineering group director at [getentity id="22032" e_name="Cadence"], Praveen Tiwari, senior manager of R&D in the verification group at [getentity id="22035" e_name="Synopsys"], Harry Foster, chief scientist at [getentity id="22017" e_name="Mentor Graphic... » read more

3D Thermal Simulation Of Resistive Heating
By Robin Bornoff - 29 Oct, 2015 - Comments: 0

Joule heating, also known as resistive or Ohmic heating, is the power lost to heat as electrical current flows down a conductor. We were introduced to Joule’s first law (Power dissipation = I²R, VI, V²/R) way back in high school. From an electronics thermal simulation perspective it requires a full 3D electrical flow simulation to be conducted, and from that the Joule heating power dissipat... » read more

10 Common Device Noise Analysis Mistakes
By Mentor, a Siemens Business - 28 Oct, 2015 - Comments: 0

Device noise is critical in nanometer-scale CMOS processes, and it fundamentally limits the performance of many circuits at 45 nm and below. Given the right tools, device noise analysis (DNA) is a fairly straightforward process that should produce results that are within 1 dB to 2 dB of silicon measurements. However, there are a number of common mistakes that can lead to grossly overestimating ... » read more

Blog Review: Oct. 28
By Jesse Allen - 28 Oct, 2015 - Comments: 0

Get up to date on the latest USB 3.1 happenings with Synopsys' Eric Huang, including the first laptops shipping with the Type C connector, the importance of USB safety, and price cuts on chips from Intel and ASMedia. The connected car is ready to hit the mass market, according to automakers, but customer adoption has been slow. Mentor's John Day takes a look at a report from the TU-Detroit c... » read more

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