tag: Siemens EDA

Will The Chip Work?
By Ed Sperling - 26 Oct, 2015 - Comments: 0

As the number of possible issues mount for integrating IP into complex chips, so does the focus on solving these issues. What becomes quickly apparent to anyone integrating multiple IP blocks is that one size doesn't fit all, either from an IP or a tools standpoint. There is no single solution because there is no single way of putting IP together. Each architecture is unique, and each brings... » read more

The Week In Review: Design/IoT
By Jesse Allen - 23 Oct, 2015 - Comments: 0

M&A ARM acquired Carbon Design Systems and its staff for an undisclosed sum, adding virtual prototyping capabilities for ARM cores. In 2008, ARM sold Carbon the tools it acquired in the 2004 purchase of virtual prototype development company AXYS Design Automation. Tools Mentor Graphics updated its PADS software, adding 3D tool capabilities to provide visualization, placement, and d... » read more

Resetting Expectations On Multi-Patterning Decomposition And Checking
By David Abercrombie - 22 Oct, 2015 - Comments: 0

It never ceases to amaze me how much confusion and misunderstanding there is when it comes to multi-patterning (MP) decomposition and checking. I sometimes forget just how new a topic it is in our industry. Because of this short-lived history, and the limited time designers have had to acquire any detailed understanding of its complexity, there appears to be some serious disconnect in expectati... » read more

Double Patterning Custom Design And Debug
By Mentor, a Siemens Business - 22 Oct, 2015 - Comments: 0

Litho-Etch-Litho-Etch (LELE) double pattern (DP) processing affects many aspects of the design flow at/below the 20 nm node level. This can be very disruptive for the custom designer, impacting basic cell design strategy, layout rules and debug as well as parasitic extraction. This paper discusses how to deal with these impacts, avoid common design mistakes, and debug quickly and accurately. ... » read more

Taming Mask Metrology
By Mark LaPedus - 22 Oct, 2015 - Comments: 0

For years the IC industry has worried about a bevy of issues with the photomask. Mask costs are the top concern, but mask complexity, write times and defect inspection are the other key issues for both optical and EUV photomasks. Now, mask metrology, the science of measuring the key parameters on the mask, is becoming a new challenge. On this front, mask makers are concerned about the critic... » read more

Blog Review: Oct. 21
By Jesse Allen - 21 Oct, 2015 - Comments: 0

Ansys' Bill Vandermark goes back to the future in this week's top five picks. Plus, the star of the world's longest hoverboard flight gets an upgrade. Perhaps the person riding it will be wearing an ocean-cleaning bikini. Straight from MemCon 2015, Rambus' Aharon Etengoff brings us a keynote exploring the increasingly blurred lines between memory and storage, and how an alternative paradigm ... » read more

Will The Chip Work?
By Ed Sperling - 19 Oct, 2015 - Comments: 1

IP is getting better, but the challenges of integrating it are getting worse. As the number of IP blocks in SoCs increases at each new process node, so does the difficulty of making them all work together. In some cases, this can mean extra code and a slight performance hit on power and performance. In other cases, it may require more drastic measures, ranging from a re-spin to a new archite... » read more

The Week In Review: Design/IoT
By Jesse Allen - 16 Oct, 2015 - Comments: 0

M&A Continuing to seek economies of scale in the IP industry, VeriSilicon and Vivante are combining forces. "This transaction creates an extensive semiconductor IP portfolio that will now include GPU cores, vision image processors, digital signal processors, video codecs, mixed signal IP and foundry foundation IP," said Wayne Dai, VeriSilicon chairman, president and CEO. The merged compa... » read more

Analog Meets Power In Standards Groups
By Ann Mutschler - 15 Oct, 2015 - Comments: 4

While the topic of language [getkc id="13" comment="Standards"] might be cringe-worthy for some, there is some noteworthy work underway in this area—particularly where power and analog meet paths. There are four main standards here: Verilog-A and Verilog-AMS VHDL-AMS SystemC-AMS SystemVerilog-AMS SystemVerilog-AMS is the newcomer, and while the standard won't be available for ... » read more

Gaps In Performance, Power Coverage
By Brian Bailey - 15 Oct, 2015 - Comments: 0

The semiconductor industry always has used metrics to define progress, and in areas such as functional verification significant advances have been made. But so far, no effective metrics have been developed for power, performance, or other system-level concerns, which basically means that design teams have to run blind. On the plus side, the industry has migrated from the use of code coverage... » read more

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