tag: Siemens EDA

Experts At The Table: ESL Reality Check
By Ed Sperling - 22 Feb, 2012 - Comments: 0

By Ed Sperling System-Level Design sat down to discuss electronic-system-level design with Stephen Bailey, director of emerging technologies for the design verification technology group at Mentor Graphics; Michael McNamara, vice president and general manager of Cadence’s System-Level Division; Ghislain Kaiser, CEO of DOCEA Power, and Shawn McCloud, vice president of marketing at Calypto. Wha... » read more

Roundtable: ESL Grows As Processes Shrink
By Ed Sperling - 22 Feb, 2012 - Comments: 0

System-Level Design talks with Steve Bailey of Mentor Graphics, Michael (Mac) McNamara of Cadence Design Systems, Ghislain Kaiser of DOCEA Power and Shawn McCloud of Calypto about what will propel growth in the system-level design tools marketplace. [youtube vid=yBhLLN40mSE] » read more

Experts At The Table: Low-Power Verification
By Ed Sperling - 17 Feb, 2012 - Comments: 0

Low-Power Engineering sat down to discuss the problems of identifying and verifying power issues with Barry Pangrle, solutions architect for low-power design at Mentor Graphics; Krishna Balachandran, director of low-power verification marketing at Synopsys; Kalar Rajendiran, senior director of marketing at eSilicon; Will Ruby, senior director of technical sales and support at Apache Design; and... » read more

Mechanical Meets Electrical
By Ed Sperling - 09 Feb, 2012 - Comments: 0

By Ed Sperling For the first part of the 20th century mechanical engineering dominated almost everything in technology. For the second half, once the transistor and the integrated circuit became well entrenched, those two disciplines largely divided up the tech market. More recently, however, they are being forced to collaborate in teams that historically had nothing in common. While the co... » read more

Margin Of Error
By Ed Sperling - 09 Feb, 2012 - Comments: 0

By Ed Sperling Adding extra circuits and silicon area to a chip has always been frowned upon by chipmakers. Extra silicon means extra money, and for most chips the least expensive is always the better choice. But at advanced process nodes, margin also can slow performance, increase power consumption, and make it harder to achieve timing closure. The obvious solution is to reduce margin thro... » read more

Step Away From the Spreadsheet
By Ed Sperling - 09 Feb, 2012 - Comments: 0

By Ann Steffora Mutschler Engineers today spend more than a quarter of their time trying to meet power specifications. A survey of more than 700 engineers by Calypto illustrates just how important and time-consuming power management is today for engineering teams. As consumer devices grow ever more complex, the need to deal with, analyze and optimize power at not just the RTL but at the sys... » read more

Experts At The Table: Low-Power Verification
By Ed Sperling - 09 Feb, 2012 - Comments: 0

Low-Power Engineering sat down to discuss the problems of identifying and verifying power issues with Barry Pangrle, solutions architect for low-power design at Mentor Graphics; Krishna Balachandran, director of low-power verification marketing at Synopsys; Kalar Rajendiran, senior director of marketing at eSilicon; Will Ruby, senior director of technical sales and support at Apache Design; and... » read more

A Brief History Of Power Formats
By Barry Pangrle - 09 Feb, 2012 - Comments: 0

Barry Pangrle A lot has happened in the industry in the way of power format standards over the past seven years. I’m going to attempt to hit on some of the highlights over that time period, especially with regards to the “Big 3” EDA vendors to hopefully put it all into better context for our readers. Early on, circa 2005, Mentor Graphics was working on a power format referred to as th... » read more

Low-Power Verification
By Ed Sperling - 08 Feb, 2012 - Comments: 0

Low-Power Engineering talks about how to verify the power portion of semiconductor designs with Krishna Balachandran of Synopsys; Barry Pangrle of Mentor Graphics; Kalar Rajendiran of eSilicon; Will Ruby of Apache Design, and Lauro Rizzatti of Eve-USA. [youtube vid=covy6ku6RgA] » read more

Experts At The Table: Making Software More Energy-Efficient
By Ed Sperling - 27 Jan, 2012 - Comments: 0

By Ed Sperling Low-Power Engineering sat down to discuss software and power with Adam Kaiser, Nucleus RTOS architect at Mentor Graphics; Pete Hardee, marketing director at Cadence; Chris Rowen, CTO of Tensilica; Vic Kulkarni, senior vice president and general manager of Apache Design, and Bill Neifert, CTO of Carbon Design Systems. What follows are excerpts of that conversation. LPE: How m... » read more

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