tag: Siemens EDA

Flexibility Vs. Portability In Emulation
By Ann Mutschler - 08 Mar, 2012 - Comments: 0

Complete and exhaustive verification of low-power designs requires a substantial effort and part of this includes running real applications on the hardware. Simulators fall short as designers realize that the so-called testbenches they create are artificial and don’t necessarily represent typical applications. As such, this is the sweet spot for emulators, also known as hardware accelerators,... » read more

Avoiding Chip Melt
By Ed Sperling - 08 Mar, 2012 - Comments: 1

By Ann Steffora Mutschler Assertions. Just the term conjures images of writing boring lines of code to feed into a simulator. But for engineering teams working at the 40nm node, the pain of making sure their verification is complete and accurate is real—and so is the potential for literally melting silicon if something goes wrong. With this in mind, ‘boring’ goes out the window and gets ... » read more

Intel vs. AMD: Who’s Right?
By Barry Pangrle - 08 Mar, 2012 - Comments: 0

By Barry Pangrle It’s all about the system. One energy-efficient component doesn’t an energy-efficient system make. There were two big announcements recently made by the industry’s two x86 designers. One was by Intel announcing its new Sandy Bridge Xeon Processor E5-2600 product family, and the other one was by AMD announcing its planned acquisition of SeaMicro. Both of these announce... » read more

Colorblind—Colorless versus Two-Color Double Patterning Design
By David Abercrombie - 05 Mar, 2012 - Comments: 0

By David Abercrombie People are always asking “What should I expect when I start designing at 20nm using double patterning?” It’s a good question, but in many real aspects, the answer is “It depends,” and that is not very satisfying to hear. The way that a designer will interact with the constraints that double patterning (DP) brings is very dependent on the design methodology used. ... » read more

Experts At The Table: ESL Reality Check
By Ed Sperling - 02 Mar, 2012 - Comments: 0

By Ed Sperling System-Level Design sat down to discuss electronic-system-level design with Stephen Bailey, director of emerging technologies for the design verification technology group at Mentor Graphics; Michael McNamara, vice president and general manager of Cadence’s System-Level Division; Ghislain Kaiser, CEO of DOCEA Power, and Shawn McCloud, vice president of marketing at Calypto. Wh... » read more

Pathfinding For Power And Heat
By Ed Sperling - 02 Mar, 2012 - Comments: 0

By Ed Sperling There are many ways to measure power and heat in an IC, and each one of them adds tremendous value to a design. But there are still holes, and those holes are just beginning to get filled. Power and heat have emerged as two of the most persistent problems in advanced designs, and there is no single or simple way to tackle either of them. Nevertheless, there is at least progre... » read more

Experts At The Table: Low-Power Verification
By Ed Sperling - 24 Feb, 2012 - Comments: 0

By Ed Sperling Low-Power Engineering sat down to discuss the problems of identifying and verifying power issues with Barry Pangrle, solutions architect for low-power design at Mentor Graphics; Krishna Balachandran, director of low-power verification marketing at Synopsys; Kalar Rajendiran, senior director of marketing at eSilicon; Will Ruby, senior director of technical sales and support at Ap... » read more

Derivative ICs: A Look At The Options
By Ed Sperling - 23 Feb, 2012 - Comments: 0

By Ann Steffora Mutschler With the cost of designing and producing even moderately advanced SoCs skyrocketing, semiconductor companies and systems houses must find ways to defray the cost across a larger number of end uses than ever. As such many companies have adopted a platform-based derivative design approach, with that the platform serving as the first SoC design of a new family. That s... » read more

Different Tradeoffs
By Ed Sperling - 23 Feb, 2012 - Comments: 0

By Ed Sperling The push to “smaller, faster and cheaper” hasn’t changed since ICs were first introduced, but the context for those requirements is beginning to shift—with enormous consequences. What was once done on multiple chips continue to migrate to a single chip or package because of cost, but in some cases the decisions about goes where go well beyond an individual device to i... » read more

Market Catches Up With Verification IP
By Ed Sperling - 23 Feb, 2012 - Comments: 0

By Ed Sperling Ever since verification IP was introduced it was seen as something that should be given away with purchased IP. The result was limited investment by IP vendors, frustration on the part of IP customers, and a market opportunity that nearly fizzled before it even began. But as the amount of commercially developed IP content continues to grow in ICs, the potential interactions ... » read more

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