tag: Siemens EDA

Fundamentals For 3D IC Flows
By Ann Mutschler - 05 Apr, 2012 - Comments: 0

While true 3D ICs are a few years off, 2.5D is here. There are some key differences, namely that with 2.5D the interposer is a passive die, but there also are some fundamental shared requirements. Samta Bansal, senior product marketing for Silicon Realization at Cadence asserted that first, the digital, custom and package environments must be seamless. “There has to be a co-design between ... » read more

Three DFM “Litho” Checkpoints at SMIC
By Mentor, a Siemens Business - 03 Apr, 2012 - Comments: 0

Design for manufacturing (DFM) has been an industry buzz word for several years, but now that it is an expected part of every design flow at 40nm and below, we are seeing how the concept of DFM can be successfully deployed. For example, Semiconductor Manufacturing International Corporation (SMIC), one of the world’s largest semiconductor foundries, has established a process for litho checking... » read more

Enterprise Power
By Ed Sperling - 30 Mar, 2012 - Comments: 0

The corporate data center is getting a lot of attention these days. ARM is fighting for a place inside server racks. Cadence has rolled out IP for faster storage standards. And Mentor Graphics has just introduced middleware for embedded Linux. Why? Because unlike the mobile space, where you need billions of units to make margins, in the corporate enterprise you only need millions. Those extr... » read more

Coherency Becomes A Stack Of Issues
By Ed Sperling - 22 Mar, 2012 - Comments: 0

By Ed Sperling As complexity increases and the industry increasingly shifts away from ASICs to SoCs, the concept of coherency is beginning to look more like a stack of issues than a discrete piece of the design. There are at least five levels of coherency that need to be considered already, with more likely to surface as stacked die become mainstream over the next few years. Perhaps even mo... » read more

The Software Side Of Derivatives
By Ed Sperling - 22 Mar, 2012 - Comments: 0

By Ann Steffora Mutschler With the options and perils associated with derivative designs well articulated today, the elephant remaining in the room is, of course, software. The software aspect of derivatives is bit muddier with some claiming the software can be maintained without modification, while others assert this is simply not possible. One indisputable fact is that software develop... » read more

SoCs Go Mainstream
By Ed Sperling - 22 Mar, 2012 - Comments: 0

By Ed Sperling The monolithic ASIC, which has been the bread-and-butter of chipmakers for decades, is giving way to systems on a chip among mainstream chipmakers and at mainstream process nodes. This shift has been overhyped, overpromised and slow to materialize. While SoCs have been common for years in mobile electronics and for high-performance platforms such as gaming consoles, they have... » read more

Cycle-Accurate Models?
By Jon McDonald - 22 Mar, 2012 - Comments: 0

By Jon McDonald I was sitting in a meeting this week and someone made the statement, “I have to have a cycle-accurate model.” This was a meeting discussing early delivery of system models for software development, performance and power analysis. The final RTL didn't even exist for the device in question, yet somehow the thinking was that a “cycle-accurate” model was required. I hear th... » read more

New Winners And Losers
By Ed Sperling - 22 Mar, 2012 - Comments: 0

The realignment of the semiconductor industry has begun, most of it beneath the radar screen. In a disaggregated supply chain, any piece in isolation looks insignificant. But taken together, these shifts begin to paint a picture of a broad realignment and refocusing of the entire industry that ultimately will cement the fortunes of some and create new winners and losers out of others. The fi... » read more

Experts At The Table: ESL Reality Check
By Ed Sperling - 09 Mar, 2012 - Comments: 0

By Ed Sperling System-Level Design sat down to discuss electronic-system-level design with Stephen Bailey, director of emerging technologies for the design verification technology group at Mentor Graphics; Michael McNamara, vice president and general manager of Cadence’s System-Level Division; Ghislain Kaiser, CEO of DOCEA Power, and Shawn McCloud, vice president of marketing at Calypto. Wh... » read more

The Trouble With Power Models
By Ed Sperling - 08 Mar, 2012 - Comments: 0

By Ed Sperling Talk with any large systems vendor about power modeling and, with very few exceptions, they’re still using a mix of spreadsheets and lower-level models—no matter how far along they are in ESL adoption and in modeling other parts of an IC. Power has crept up on even the biggest companies, which have never really figured out how to implement it into their design flows. For ... » read more

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