tag: Siemens EDA

Gap Vs. Gap
By Ed Sperling - 26 Apr, 2012 - Comments: 0

By Ed Sperling Among tools vendors it’s been standard practice to listen closely to customers but not deliver everything they ask for—or at least not always on the customers’ timetable. This strategy has worked well enough for both sides in the past, but at 20nm and in stacked die configurations, the level of tension between these two worlds is increasing, and the gaps in the tool cha... » read more

Rethinking Timing Optimization
By Ed Sperling - 26 Apr, 2012 - Comments: 0

By Ann Steffora Mutschler As semiconductor manufacturing technology continues its march toward 20nm, SoCs are plagued with advanced interconnect delays, cross capacitance, and process variability, as well as area and power constraints—and the significance of these factors is increasing with each passing node. “With lower nodes we are getting advantage on area, more and more logic is get... » read more

From Cryptic Error Messages To Contradictory Commands
By Ed Sperling - 26 Apr, 2012 - Comments: 0

By Ann Steffora Mutschler For the past 30 years, semiconductor designers have increasingly relied on automated CAD tools to complete their projects. Over time, these tools have indeed improved from a functionality perspective, but sometimes usability has not kept up with users’ needs. Depending on which tools and what type of use, some tools are easier to use than others, according to Mik... » read more

Boosting Yield With Layout Awareness
By Ed Sperling - 26 Apr, 2012 - Comments: 0

By Ann Steffora Mutschler Yield. Just the word can make many engineers cringe and hide in their cubicles—especially with manufacturing problems and excessive power during test increasing causing failures. But the combination of physical data with diagnostics engines may be the light at the end of the tunnel, allowing for easier pinpointing of defects. There are many reasons why a chip fai... » read more

Smarter Design Strategies
By Jon McDonald - 26 Apr, 2012 - Comments: 0

By Jon McDonald I had an interesting discussion with a customer recently. They were involved in the architectural specification of a fairly complex piece of silicon. They spent a significant amount of time designing the part to work under worst-case power characteristics and defining the power supply requirements for the device in this worst-case use mode. The conversation started with the ... » read more

Roundtable: Bridging Hardware And Software
By Ed Sperling - 25 Apr, 2012 - Comments: 0

System-Level Design talks about where the problems are with hardware-software co-design and how much progress we've made with Narendra Konda of Nvidia, Frank Schirrmeister of Cadence, Shabtay Matalon of Mentor Graphics, Kurt Shuler of Arteris and Jack Greenbaum of Green HIlls Software. [youtube vid=EOUPsDOYGq8] » read more

Finite Math
By Ed Sperling - 13 Apr, 2012 - Comments: 0

In his keynote speech at the Mentor User-To-User conference yesterday, Sameer Halepete, Nvidia’s vice president of LSI engineering, made a very interesting point. At all levels of computing, from smartphones to the data center, the power budget is fixed, and the old ways of addressing it aren’t working. What that means is that there will not be a single solution to reducing power. It ca... » read more

2.5D Leverages Existing Tools On The Way To 3D
By Ed Sperling - 05 Apr, 2012 - Comments: 0

By Ann Steffora Mutschler As design and manufacturing issues with true 3D design continue to be worked out, interim 2.5D technologies are moving ahead as engineering teams leverage this packaging-driven approach to manage heat, cost, area and yield. Technologies such as Wide I/O memory support 2.5D, and when combined with logic they allow engineering teams to realize a performance increase,... » read more

Getting Ready For Stacked Die
By Ed Sperling - 05 Apr, 2012 - Comments: 0

By Ed Sperling The move toward stacking of die has always been a series of disconnected pieces and vague promises for the future, but in the past few months the scenario has changed radically—and so has the commentary. All three of the Big Three EDA vendors now have at least some of the pieces in place for 2.5D stacking and are working on a full 3D flow. Two of the biggest FPGA vendors, A... » read more

FinFET Vs. Tri-Gate
By Barry Pangrle - 05 Apr, 2012 - Comments: 0

By Barry Pangrle A large portion of the Common Platform Technology Forum, recently held in Santa Clara, was dedicated to presentations about 14nm process technologies and FinFETS. If you missed the event and are interested, many of the presentations are available from a link off of the Common Platform home page. Dick James wrote a nice article about GlobalFoundries’ claim that its FinFETS ar... » read more

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