Getting Ahead Of Yourself


By Jon McDonald Recently we've been doing some minor remodeling in our house—nothing requiring major contractors. It’s mostly smaller things that unfortunately require a significant amount of personal involvement. Over the course of the past few weeks we've had a number of "projects" that we've started, then had to undo what was done because we were interfering with another area of work. M... » read more

Understanding Via Effects


As the demand for fast computation and information transmission has increased dramatically in recent years, many designs have boards with signals operating in the multiple-Gbps range. Advanced memory designs are targeting over 10 Gbps data rates while the SERDES standard is moving toward 25-28 Gbps. With the signal speed changes come the new challenges of solving design issues never seen before... » read more

Technology Crossover Ahead


The attention showered upon NVM Express these days by both Synopsys (verification IP) and Cadence (subsystem) is significant. It’s the first significant opening in the enterprise computing space to emerge in years, and this is a market in which efficiency and performance are both measured and fully recognized. While SoC developers in the mobile space continue to develop power-management ca... » read more

Experts At The Table: Hardware-Software Co-Design


By Ed Sperling System-Level Design sat down to discuss hardware-software co-design with Frank Schirrmeister, group marketing director for Cadence’s System and Software Realization Group; Shabtay Matalon, ESL market development manager at Mentor Graphics; Kurt Shuler, vice president of marketing at Arteris; Narendra Konda, director of hardware engineering at Nvdia; and Jack Greenbaum, direct... » read more

Old Problem, New Solutions


By Ann Steffora Mutschler Electromigration (EM) and electrostatic discharge (ESD) may not be new, but design design sophistication and tiny wires are demanding that engineering teams take a fresh look and utilize new tools to lesson the impacts of damaging electrical events. “These are certainly not new phenomenon,” said Carey Robertson, director of product marketing for Calibre at Ment... » read more

Traversing The Abstraction Landscape


By Ann Steffora Mutschler Back in the early days of semiconductor design engineers could count the number of transistors on their chip with their own two eyes. They designed and worked at the same level of design abstraction when doing the timing analysis. Tools were SPICE-like, maybe abstracted with slightly simpler timing models than the SPICE-level transistor models. Thanks to Moore’... » read more

Intel’s Hot New Tri-Gate Processors


By Barry Pangrle Intel announced its newest third-generation Core processors on April 23rd. There has been much anticipation surrounding these new chips from Intel, largely because of their new 22nm tri-gate process technology used to fabricate these devices. Figure 1, from the presentation entitled, “Intel’s Revolutionary 22nm Transistor Technology,” by Mark Bohr and Kaizad Mistry, s... » read more

Experts At The Table: Hardware-Software Co-Design


By Ed Sperling System-Level Design sat down to discuss hardware-software co-design with Frank Schirrmeister, group marketing director for Cadence’s System and Software Realization Group; Shabtay Matalon, ESL market development manager at Mentor Graphics; Kurt Shuler, vice president of marketing at Arteris; Narendra Konda, director of hardware engineering at Nvdia; and Jack Greenbaum, directo... » read more

Anchors Away – Anchoring and Seeding in Double Pattern Design.


David Abercrombie Many aspects of how double patterning (DP) affects the designer depend on the methodology used and the level of control the designer wants. One extreme in methodology and control is full two-layer design, in which the designer decomposes the entire design and tapes out two masks. The designer has complete control of the coloring, but all the responsibility and work as well. T... » read more

Experts At The Table: Hardware-Software Co-Design


By Ed Sperling System-Level Design sat down to discuss hardware-software co-design with Frank Schirrmeister, group marketing director for Cadence’s System and Software Realization Group; Shabtay Matalon, ESL market development manager at Mentor Graphics; Kurt Shuler, vice president of marketing at Arteris; Narendra Konda, director of hardware engineering at Nvdia; and Jack Greenbaum, directo... » read more

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