Measuring FinFETs Will Get Harder


The industry is gradually migrating toward chips based on finFET transistors at 16nm/14nm and beyond, but manufacturing those finFETs is proving to be a daunting challenge in the fab. Patterning is the most difficult process for finFETs. But another process, metrology, is fast becoming one of the biggest challenges for the next-generation transistor technology. In fact, [getkc id="252" kc_n... » read more

It’s a Materials World, With Positive Forecast


By Michael Fury What’s the latest in materials forecasts for ALD/CVD precursors, CMP consumables, electronic gases, silicon wafers and sputtering targets? Techcet gives us an update. Metal Gate and Electrode Precursors to Double in Five Years Use of front-end Ta and W metal gate and Hf gate dielectric precursors will grow over 2.5x by 2020, according to a new report from Techcet, “20... » read more

What Will 7nm And 5nm Look Like?


Citing an assortment of undisclosed manufacturing issues, Intel in July pushed out the introduction of its 10nm chip and process technology to the second half of 2017. This is roughly six or more months later than expected. With the delay at 10nm, [getentity id="22846" e_name="Intel"] also pushed out its process cadence from 2 to 2.5 years. Other foundries, meanwhile, are struggling to keep ... » read more

5 Technologies To Watch


The industry is developing a dizzying array of new technologies. In fact, there are more new and innovative technologies than ever before. And the list is countless. At least from my vantage point, I have come up with my own list of the top five technologies to watch in 2015 and beyond. They are listed in alphabetical order. (See below). Obviously, there are more than just five technologi... » read more

The Week In Review: Manufacturing


For years, Altera’s sole foundry was TSMC. Then, not long ago, Altera selected Intel as its foundry partner for 14nm. TSMC still handles 20nm and above work for Altera. Now, Altera will soon select a foundry partner for 10nm. “Altera will make a decision on which foundry partner it will choose for 10nm finFET at the end of 1Q15, noting it will decide between Intel and TSMC,” said John Vin... » read more

Unraveling The Mysteries At IEDM


In some respects, the 2014 IEEE International Electron Devices Meeting (IEDM) was no different than past events. The event, held this week in San Francisco, included the usual and dizzying array of tutorials, sessions, papers and panels. On the leading-edge CMOS front, for example, the topics included [getkc id="82" kc_name="2.5D"]/[getkc id="42" kc_name="3D IC"] chips, III-V materials, [getkc ... » read more

IBM, Intel And TSMC Roll Out finFETs


At the IEEE International Electron Devices Meeting (IEDM) in San Franciso, IBM, Intel and Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) this week will separately present the latest details of their respective 16nm/14nm finFET technologies. As expected, Intel and TSMC will continue to use bulk CMOS. IBM will continue to go with rival silicon-on-insulator (SOI) technology. At IEDM, Intel ... » read more

Blog Review: Oct. 22


What is UX? The User Experience, of course. Rambus' Aharon Etengoff notes that the IoT UX is now the subject of a Harvard Business Review article. A long list of hurdles are expected at the 10nm process node, including multiple levels of local interconnects, more complex layout rules, timing problems, and a slew of others. Cadence's Richard Goering puts it all in perspective. Mentor's R... » read more

The Week In Review: Manufacturing


It’s official: IBM appears to be exiting the chip business. After months of talks, IBM has agreed to pay GlobalFoundries $1.5 billion to take Big Blue’s chip unit off its hands, according to reports from Bloomberg. IBM will also receive $200 million worth of assets, according to the reports. At the upcoming IEEE International Electron Devices Meeting (IEDM), Intel and IBM will present... » read more

Time To Look At SOI Again


Chipmakers have the luxury of looking at several process options when developing chips at the 28nm node and beyond. Using bulk CMOS, for example, chipmakers can scale planar transistors down to 20nm. Then, at 20nm, planar runs out of gas due to the so-called short-channel effect. At that point, IC makers must migrate towards finFETs at 16nm/14nm and beyond. Another process option is fully... » read more

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