tag: stacked die

Is The 2.5D Supply Chain Ready?
By Ed Sperling - 28 Sep, 2015 - Comments: 0

A handful of big semiconductor companies began taking the wraps off 2.5D and fan-out packaging plans in the past couple of weeks, setting the stage for the first major shift away from Moore's Law in 50 years. Those moves coincide with reports of commercial [getkc id="82" kc_name="2.5D"] chips from chip assemblers and foundries that are now under development. There have been indications for... » read more

Is HW Or SW Running the Show?
By Brian Bailey - 24 Sep, 2015 - Comments: 1

In the past, hardware was designed and then passed over to the software team for them to add their contribution to the product. This worked when the amount of software content was small and the practice did not significantly contribute to product delays. Over time, the software content grew and today it is generally accepted that software accounts for more product expense than hardware, takes l... » read more

Raise A Fence, Dig A Tunnel, Build A Bridge
By Ed Sperling - 17 Sep, 2015 - Comments: 0

There are three main options for chipmakers over the course of the next decade. Which option they choose depends upon their individual needs, talents, and how much and what kind of differentiation they believe will matter to them. The options roughly fall into three categories—fence, bridge or tunnel. The fence option Rather than changing anything, the entire ecosystem can stick to wha... » read more

SEMICON Taiwan’s Packaging Punch
By SEMI - 17 Sep, 2015 - Comments: 0

SEMICON Taiwan packed a punch, setting several new records and new heights in 2015. This year marked the 20th anniversary of SEMICON in Taiwan and was the largest SEMICON in Taiwan ever, with a Nobel Prize winner (Professor Shuji Nakamura, 2014’s winner) keynoting the Executive Summit, Taiwan’s President Ma speaking at the hugely attended Gala Dinner, and 2015 on track for TSMC to be the wo... » read more

We Must Teach Chips To Feel Pain
By Imec - 17 Sep, 2015 - Comments: 0

By Guido Groeseneken When I was a doctorate student in the 1980s there was lots of wild speculation about Moore’s Law: give it another 10 years and transistors will stop getting smaller, they were saying back then. But in the end, the creativity of engineers turned out to be greater than the pessimism of the forecasters. Yet today I believe that we are close to the end of Moore’s Law.... » read more

New Options For Power
By Ed Sperling - 10 Sep, 2015 - Comments: 0

Chipmakers have been talking for years about the next big breakthrough in battery technology, low-power architectures and energy harvesting. So far, none of them has made their job any easier. Batteries empty out too quickly, and the technology for improving the amount of energy that can be stored don't improve fast enough—or safely enough when they do show big improvements—to make a big... » read more

Challenges At Advanced Nodes
By Ed Sperling - 09 Sep, 2015 - Comments: 0

Semiconductor Engineering sat down to discuss finFETs, 22nm FD-SOI and how the how the market will segment over the next few years with Marie Semeria, CEO of [getentity id="22192" e_name="Leti"]; Patrick Soheili, vice president of product management and corporate development at [getentity id="22242" e_name="eSilicon"]; Paul Boudre, CEO of Soitec; and Subramani Kengeri, vice president of global ... » read more

Rethinking Differentiation
By Ed Sperling - 28 Aug, 2015 - Comments: 0

Differentiation is becoming more difficult, more time-consuming, and in some cases much more expensive for chipmakers. The traditional metrics of faster performance, lower power and less area/cost, which are leftovers from the PC era, no longer are a guarantee of success despite the fact that they are still baseline metrics for many designs. Even new metrics such as ecosystem completeness, w... » read more

Electronics Butterfly Effect
By Brian Bailey - 27 Aug, 2015 - Comments: 1

Everyone has heard of the butterfly effect where a small change in a non-linear system can result in large difference in an outcome. For the past 40 years, the electronics industry has approximated a linear system, fed primarily by Moore’s Law. The incremental changes available at each new process node have led us to make incremental changes and improvements in many aspects of the design, its... » read more

Interconnect Challenges Grow
By Mark LaPedus - 20 Aug, 2015 - Comments: 1

It’s becoming apparent that traditional chip scaling is slowing down. The 16nm/14nm logic node took longer than expected to unfold. And the 10nm node and beyond could suffer the same fate. So what’s the main cause? It’s hard to pinpoint the problem, although many blame the issues on lithography. But what could eventually hold up the scaling train, and undo Moore’s Law, is arguably t... » read more

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