tag: statistical analysis

Virtuoso ADE Assembler
By Cadence - 26 May, 2021 - Comments: 0

Cadence Virtuoso ADE Assembler is an advanced design and simulation environment that extends the capabilities of Virtuoso ADE Explorer, adding all the tests needed to fully verify a design over all operational, process, and environmental conditions. As more analysis is required, users can take incremental advantage of the Virtuoso Variation Option to do more advanced statistical analysis on the... » read more

A New Co-Simulation Approach for Tolerance Analysis on Vehicle Propulsion Subsystem
By Synopsys - 06 May, 2020 - Comments: 0

An increasing demand for reducing cost and time effort of the design process via improved CAE (ComputerAided Engineer) tools and methods has characterized the automotive industry over the past two decades. One of the main challenges involves the effective simulation of a vehicle’s propulsion system dealing with different physical domains: several examples have been proposed in the literature ... » read more

New Advancements in Using Statistical Models as Part of a Standard MEMS Design Flow
By Coventor - 19 Jun, 2019 - Comments: 0

This paper presents the benefits of using statistical models during MEMS design, through the virtual reproduction of a test structure for measuring a beam’s pull-in voltage. This electrical measurement is used as a functional indicator of the process quality for manufactured wafers. Statistical variations of process parameters (material properties, silicon thickness, sidewall angle and edge s... » read more

Using Advanced Statistical Analysis To Improve FinFET Transistor Performance
By Jimmy Gu - 21 Sep, 2017 - Comments: 0

Trial and error wafer fabrication is commonly used to study the effect of process changes in the development of FinFET and other advanced semiconductor technologies. Due to the interaction of upstream unit process parameters (such as deposition conformality, etch anisotropy, selectivity) during actual fabrication, variations based upon process changes can be highly complex. Process simulators t... » read more

Optimization Challenges For 10nm And 7nm
By Brian Bailey - 11 Aug, 2016 - Comments: 0

Optimization used to be a simple timing against area tradeoff, but not anymore. As we go to each new node the tradeoffs become more complicated, involving additional aspects of the design that used to be dealt with in isolation. Semiconductor Engineering sat down to discuss these issues with Krishna Balachandran, director of product management for low-power products at [getentity id="22032"... » read more

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