Virtuoso ADE Assembler

By Cadence - 26 May, 2021 - Comments: 0

Cadence Virtuoso ADE Assembler is an advanced design and simulation environment that extends the capabilities of Virtuoso ADE Explorer, adding all the tests needed to fully verify a design over all operational, process, and environmental conditions. As more analysis is required, users can take incremental advantage of the Virtuoso Variation Option to do more advanced statistical analysis on the... » read more

A New Co-Simulation Approach for Tolerance Analysis on Vehicle Propulsion Subsystem

By Synopsys - 06 May, 2020 - Comments: 0

An increasing demand for reducing cost and time effort of the design process via improved CAE (ComputerAided Engineer) tools and methods has characterized the automotive industry over the past two decades. One of the main challenges involves the effective simulation of a vehicle’s propulsion system dealing with different physical domains: several examples have been proposed in the literature ... » read more

New Advancements in Using Statistical Models as Part of a Standard MEMS Design Flow

By Coventor - 19 Jun, 2019 - Comments: 0

This paper presents the benefits of using statistical models during MEMS design, through the virtual reproduction of a test structure for measuring a beam’s pull-in voltage. This electrical measurement is used as a functional indicator of the process quality for manufactured wafers. Statistical variations of process parameters (material properties, silicon thickness, sidewall angle and edge s... » read more

Using Advanced Statistical Analysis To Improve FinFET Transistor Performance

By Jimmy Gu - 21 Sep, 2017 - Comments: 0

Trial and error wafer fabrication is commonly used to study the effect of process changes in the development of FinFET and other advanced semiconductor technologies. Due to the interaction of upstream unit process parameters (such as deposition conformality, etch anisotropy, selectivity) during actual fabrication, variations based upon process changes can be highly complex. Process simulators t... » read more

Optimization Challenges For 10nm And 7nm

By Brian Bailey - 11 Aug, 2016 - Comments: 0

Optimization used to be a simple timing against area tradeoff, but not anymore. As we go to each new node the tradeoffs become more complicated, involving additional aspects of the design that used to be dealt with in isolation. Semiconductor Engineering sat down to discuss these issues with Krishna Balachandran, director of product management for low-power products at [getentity id="22032"... » read more

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

tag: statistical analysis

Virtuoso ADE Assembler

A New Co-Simulation Approach for Tolerance Analysis on Vehicle Propulsion Subsystem

New Advancements in Using Statistical Models as Part of a Standard MEMS Design Flow

Using Advanced Statistical Analysis To Improve FinFET Transistor Performance

Optimization Challenges For 10nm And 7nm