tag: STMicroelectronics

A Smart Filling Solution Yields Multiple Benefits
By Mentor Graphics Staff Writers - 01 Jul, 2011 - Comments: 0

By Jeff Wilson, A return on investment doesn’t happen until customers actually buy your product, so the most fundamental goal for designers is getting their designs to market. While there are numerous steps along the way, one task that must be performed is adding fill to the design. Fill is like design rule checking (DRC)—it’s not an optional step, because it is needed to ensure the manu... » read more

Tri-Gate’s Fallout
By Ed Sperling - 26 May, 2011 - Comments: 0

By David Lammers Intel Corp. dropped a rock into the pond of transistor technology when it announced its 22nm tri-gate technology in San Francisco earlier this month. The ripples continue to move out from that event, with impacts on IDMs, foundries, and fabless semiconductor companies being closely studied. Now that Intel has come out of the closet with its tri-gate technology, “the found... » read more

The Multiple Faces Of Virtual Prototyping
By Ann Mutschler - 28 Apr, 2011 - Comments: 0

Virtual prototyping conjures either confusion or relief, so it should come as no surprise that some chip designers are still confused about the different types of prototypes on the market. “Virtual prototyping is going through a change right now,” explained Gary Smith, founder and chief analyst for Gary Smith EDA. “Today, users are using cycle-based tools to prototype sections of their... » read more

Gene’s Law Meets EDA
By Ed Sperling - 17 Mar, 2011 - Comments: 0

By Pallab Chatterjee What will be the next major improvement that will cut power levels by an order of magnitude? That question was the basis of a roundtable discussion at the recent ISSC conference. Current technology provides incremental improvements each year, but the next generation of electronic systems will require dramatic changes and innovation. This premise is based on Gene’s Law... » read more

Experts At The Table: Concurrent Design
By Ed Sperling - 25 Feb, 2011 - Comments: 0

Low-Power Engineering sat down with Marco Brambilla, ASIC design manager at STMicroelectronics; Charlie Janac, president and CEO of Arteris; Mike Gianfagna, vice president of marketing at Atrenta, and Javier DeLaCruz, director of semiconductor packaging at eSilicon. What follows are excerpts of that discussion. LPE: Is concurrent design strategic—meaning is it done at the architectural lev... » read more

Experts At The Table: Concurrent Design
By Ed Sperling - 18 Feb, 2011 - Comments: 0

Low-Power Engineering sat down with Marco Brambilla, ASIC design manager at STMicroelectronics; Charlie Janac, president and CEO of Arteris; Mike Gianfagna, vice president of marketing at Atrenta, and Javier DeLaCruz, director of semiconductor packaging at eSilicon. What follows are excerpts of that discussion. LPE: Is there cross-training going on to allow for concurrent design? Brambilla... » read more

Concurrent Design
By Ed Sperling - 11 Feb, 2011 - Comments: 0

The idea of developing software and hardware simultaneously isn't new, but it has taken on renewed urgency in IC design because of growing complexity, including power and proximity issues. Low-Power Engineering captures the perspective of executives at four companies working in this market: Marco Brambilla of STMicroelectronics; Charlie Janac of Arteris; Mike Gianfagna of Atrenta, and Javier De... » read more

Healthy Living Electronics Dominated By Power
By Ed Sperling - 10 Feb, 2011 - Comments: 0

By Pallab Chatterjee The theme for this years ISSCC (International Solid State Circuits Conference) is “Electronics for Healthy Living.” In addition to the new microprocessors, memory and data converter technologies, the focus and keynotes are directed toward health-care products. The common theme between all the talks is that health-care is being driven by mobility, information flow, a... » read more

Experts At The Table: Concurrent Design
By Ed Sperling - 10 Feb, 2011 - Comments: 0

Low-Power Engineering sat down with Marco Brambilla, ASIC design manager at STMicroelectronics; Charlie Janac, president and CEO of Arteris; Mike Gianfagna, vice president of marketing at Atrenta, and Javier DeLaCruz, director of semiconductor packaging at eSilicon. What follows are excerpts of that discussion. LPE: What is concurrent design and how has the definition changed? DeLaCruz: Th... » read more

Version Control Nightmares
By Ed Sperling - 16 Dec, 2010 - Comments: 0

By Ed Sperling The rampant re-use of IP and the growing reliance on software to smooth over glitches is creating a nightmare in version control of everything from IP blocks to EDA tools. Version control has always been a problem in SoC design, of course. Tools have to be in sync with engineering teams that are spread across multiple continents and working on different pieces of the design e... » read more

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