tag: STMicroelectronics

What’s ST’s FD-SOI Technology All About?
By Various Writers - 22 Jun, 2012 - Comments: 0

As I blogged here on SemiMD last week, STMicroelectronics has announced that to supplement in-house production at their fab in Crolles, the company has tapped GlobalFoundries for high-volume production of 28nm then 20nm FD-SOI mobile devices.  ST will also open access to its FD-SOI technology to GlobalFoundries’ other customers.  High-volume manufacturing will kick off with ST-Ericsson’s ... » read more

Consortium Results (Part 3 of 3): 20nm FDSOI Comes Out Way Ahead
By Various Writers - 27 Mar, 2012 - Comments: 0

The results of the most recent SOI Consortium benchmarking study detail the interest of planar FD-SOI as early as the 28nm and 20nm technology nodes, in terms of performance, power and manufacturability. This 3-part blog series looks further at some of the implications. ~~ The SOI Industry Consortium announcement at the end of the year provided silicon proof that FD-SOI handily bea... » read more

FD-SOI – Consortium Results (Part 2 of 3): Power and Performance
By Various Writers - 21 Mar, 2012 - Comments: 0

The results of the most recent SOI Consortium benchmarking study detail the interest of planar FD-SOI as early as the 28nm and 20nm technology nodes, in terms of performance, power and manufacturability. This 3-part blog series looks further at some of the implications. ~~ Fully depleted transistor architectures such as Planar FD-SOI, FinFETs (which is also a fully-depleted technolog... » read more

FD-SOI Workshop ppts – STM’s 1st 28nm FD-SOI product line
By Various Writers - 12 Mar, 2012 - Comments: 0

The SOI Consortium’s 6th FD-SOI workshop, held just after ISSCC, yielded some exciting news. Most of the presentations are freely available for downloading from the SOI Consortium website. Here are the highlights. STMicroelectronics In a terrific presentation by Giorgio Cesana, Marketing Director at STMicroelectronics, he revealed that the company would be releasing a major product line b... » read more

FD-SOI – Recent Consortium Results (Part 1 of 3): Manufacturing
By Various Writers - 05 Mar, 2012 - Comments: 0

The most recent SOI Consortium benchmarking study regarding 28nm and 20nm FD-SOI results (silicon-calibrated simulations at the 28nm node of complex circuits including ARM cores and DDR3 memory controllers) covered a lot of ground. This post is part 1 of a 3-part blog series that will be highlighting key points with respect to: 1. manufacturing; 2. power & performance; 3. 20nm benchmarking ... » read more

Model Report Card
By Ed Sperling - 26 Jan, 2012 - Comments: 0

By Ann Steffora Mutschler From its perspective as a leader implementing system level design methodology, STMicroelectronics is uniquely positioned to discuss issues and challenges related to the use of models in a variety of use cases. System-Level Design had the opportunity recently to discuss challenges in the modeling space with Jean-Marc Chateau, director of ST’s SPT (System Platforms a... » read more

Playing The Voltage Game
By Ed Sperling - 01 Dec, 2011 - Comments: 0

y Ed Sperling Scaling down the voltage to boost battery life and cut energy costs has always been considered the best option, but it’s getting more difficult at advanced nodes and in stacked die packages. The key problems are noise and leakage. Lowering the voltage exacerbates both of them, forcing a rethinking of the whole design process starting at the architectural level and continuing... » read more

Thermal Modeling Held Back By Outdated Standards
By Ed Sperling - 06 Oct, 2011 - Comments: 0

By Ann Steffora Mutschler As the reality of true 3D IC design nears, engineering teams are keen to manage the heat between the stacked die in order to avoid catastrophic failures. Thermal modeling tops the roster of techniques to leverage in this area. Herve Jaouen, director of modeling and simulation in STMicroelectronics’ technology R&D organization, explained that in 3D designs the... » read more

Customer Perspective: STMicroelectronics
By Ed Sperling - 11 Aug, 2011 - Comments: 0

By Ed Sperling Philippe Magarshack, group vice president for technology R&D at STMicroelectronics, sat down with Low-Power Engineering to talk about some of the fundamental changes ahead in how SoCs are designed, built, how they perform and what steps can be taken to speed time to market. LPE: What do you see as the biggest changes ahead? Magarshack: One is the sheer size of the ecosy... » read more

Customer perspective: STMicroelectronics
By Ed Sperling - 21 Jul, 2011 - Comments: 0

By Ann Mutschler With eight SoC designs currently in development on its 28nm manufacturing process, STMicroelectronics is well acquainted with the power challenges of making those designs work. LPE discussed these issues with Philippe Magarshack, ST’s Technology R&D Group Vice-President. What follows are excerpts of that conversation. LPE: What are the biggest challenges in getting ST... » read more

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