Blog Review: Sept. 7


Cadence's Paul McLellan shares highlights from the recent Hot Chips tutorial on CXL and how enhanced memory pooling enables new memory usage models as CXL 3.0 approaches the same speed as DRAM. Synopsys' Sam Tennent and Kamal Desai highlight the emergence of virtual prototyping, its synergy with continuous integration and development setups, and the benefits when these disciplines are combin... » read more

Challenges Mount In New Autos


Electronics are becoming the primary differentiator for carmakers, adding an array of options that can alter everything from how a vehicle's occupants interact with their surroundings to how the vehicle drives. But the infrastructure needed to support these features also raises a slew of technology and business questions for which there are no simple answers today. For example, how will new ... » read more

Week In Review: Design, Low Power


Trade regulations/legal The U.S. government placed new restrictions on sales of GPUs to China that could be used for high-performance computing, artificial intelligence, and other advanced applications. NVIDIA said in an SEC filing Wednesday that officials told the company it must seek an export license for sales to China or Russia of its A100 and H100 chips, and any system that includes those... » read more

Improving Safety And Security For Tomorrow’s Autonomous Vehicles


With the evolution of autonomous vehicles, today’s cars are becoming both more connected and complex. Consumers and suppliers worldwide are demanding much more intelligence and customization, which adds pressure on product development teams to validate the underlying technology and start their design processes months earlier. Enhancements in hardware and software features also mean that the w... » read more

Driver Monitoring Raises Complexity, Adds Privacy Concerns


While you watch the road, your car may be watching you back. The automotive industry’s transition toward self-driving technology means cars increasingly are equipped with features that measure driver alertness and engagement, among many other data points. Executives say such features save lives and spur innovation, while simultaneously raising significant technical, legal, and ethical questio... » read more

Design For Security Now Essential For Chips, Systems


It's nearly impossible to create a completely secure chip or system, but much can be done to raise the level of confidence about that security. In the past, security was something of an afterthought, disconnected from the architecture and added late in the design cycle. But as chips are used increasingly in safety- and mission-critical systems, and as the value of data continues to rise, the... » read more

Blog Review: Aug. 31


Cadence's Paul McLellan wonders what's happened to 450mm wafers as equipment development efforts end, the only wafer fab is decommissioned, and manufacturers see little likelihood to recoup further investment in R&D. Synopsys' Manuel Mota finds that the scale and modular flexibility of chiplets can help meet narrowing time-to-market windows and looks at how UCIe provides a complete stack... » read more

ECO Should Not Stand For Extended Challenge Order


There’s an old saying that the first 90% of a task takes 90% of the schedule, and the remaining 10% takes the other 90% of the time. In chip development, design-signoff closure has become one such task. Ideally, when the design has been placed and routed (physical implementation), final analysis of timing and other metrics is performed and an engineering change order (ECO) file is issued to t... » read more

Is There A Limit To The Number of Layers In 3D-NAND?


Memory vendors are racing to add more layers to 3D NAND, a competitive market driven by the explosion in data and the need for higher-capacity solid state drives and faster access time. Micron already is filling orders for 232-layer NAND, and not to be outdone, SK Hynix announced that it will begin volume manufacturing 238-layer 512Gb triple level cell (TLC) 4D NAND in the first half of next... » read more

Blog Review: Aug. 24


Synopsys' Manuel Mota presents an overview of some of the newest multi-chip module packaging types and their advantages and disadvantages for different kinds of applications, as well as the importance of die-to-die interfaces. Cadence's Steve Brown finds that innovative products require that electronics be analyzed in the context of the environment in which they run, making mechanical and el... » read more

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