Blog Review: Jan. 30


Cadence's Paul McLellan provides a primer on embedded memory types, their tradeoffs, and the emerging technologies to keep an eye on. Mentor's Matthew Ballance takes a look at how Portable Stimulus can help create better virtual sequences. Synopsys' Taylor Armerding takes a look at what the next year holds for open source, from changes in license terms to the impact of GDPR and a broader ... » read more

A Simplified Way to Debug IIP Designs and SoC


Design problems that appear in the late phases of the development cycle can be extremely difficult to track down and debug, thus putting project schedules at risk. It's not uncommon for an engineer to run the verification test on what appears to be the main design problem, only to find the problem in the dump. Traditional debug techniques don't always help to localize the issue. This whitepaper... » read more

Week In Review: Design, Low Power


M&A Ansys will acquire Helic, a provider of electromagnetic crosstalk analysis and signoff tools. Founded in 2000, Helic's tools included pre- and post-LVS EM modeling, inductor synthesis and modeling, and analysis of crosstalk risk. The company's technology will be integrated into a solution for on-chip, 3D integrated circuit and chip-package-system electromagnetics and noise analysis. Th... » read more

Week in Review: IoT, Security, Auto


Internet of Things Tony Franklin, Intel’s general manager for Internet of Things Segments, is interviewed by Lorin Fries on how the chipmaker is helping to develop smart farming applications. “We focus primarily on high-performance computer technologies, as well as communication technologies, which have great applicability for food systems. We work closely with a broad ecosystem of partner... » read more

Variation Issues Grow Wider And Deeper


Variation is becoming more problematic as chips become increasingly heterogeneous and as they are used in new applications and different locations, sparking concerns about how to solve these issues and what the full impact will be. In the past, variation in semiconductors was considered a foundry issue, typically at the most advanced process node, and largely ignored by most companies. New p... » read more

Blog Review: Jan. 23


Synopsys' Taylor Armerding investigates what's happened with the Stuxnet malware since 2010, when it destroyed hundreds of centrifuges at an Iranian nuclear enrichment facility. Cadence's Paul McLellan provides an update on the current state of EUV and what's needed to make high-volume manufacturing possible. In a video, Mentor's Colin Walls explains software's role in embedded system pow... » read more

Power Issues Rising For New Applications


Managing power in chips is becoming more difficult across a wide range of applications and process nodes, forcing chipmakers and systems companies to rethink their power strategies and address problems much earlier than in the past. While power has long been a major focus in the mobile space, power-related issues now are spreading well beyond phones and laptop computers. There are several re... » read more

Week in Review: IoT, Security, Auto


Internet of Things A dairy barn without any people working in it. An automated greenhouse for produce. Coming soon, little robots that will weed crop fields and look for diseased plants. This is Rivendale Farms, in the countryside west of Pittsburgh, which is 175 acres serving as a beta site for agricultural Internet of Things technology. The small farm has about 150 Jersey cows, each of which... » read more

Week In Review: Design, Low Power


M&A Rambus acquired the assets of Diablo Technologies. Founded in 2003, Diablo Technologies specialized in NVDIMM technologies, but was hit with a patent lawsuit by Netlist in 2013. While Diablo won the lawsuit and several subsequent appeals, it declared bankruptcy in December 2017. Rambus says the technology will provide a foundation for integrating existing DRAM and Flash along with emer... » read more

Efficient Hierarchical Verification For Low Power Designs


By Susantha Wijesekara and Himanshu Bhatt Growing design sizes, low power (LP) complexity and the need for early stage verification is making designers adopt hierarchical verification flows. Traditionally for hierarchical verification, designers use a black box, liberty model based hierarchical flow, timing model (ETM) flow or stub/glass box flows that offer various degrees of trade-offs for... » read more

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