tag: Synopsys

Week in Review: IoT, Security, Auto
By Jeff Dorsch - 14 Dec, 2018 - Comments: 0

Internet of Things Arm made five 2019 predictions for the Internet of Things. They are: The intelligent home goes mainstream; personalized delivery options; improved health-care service; smart cities seek to improve revenue streams and citizen engagement; and smart buildings use more technology for efficiencies. The company also commissioned a worldwide survey of 2,000 consumers, conducted by ... » read more

Week In Review: Design, Low Power
By Jesse Allen - 14 Dec, 2018 - Comments: 0

The MIPI Alliance released MIPI I3C Basic v1.0, a subset of the MIPI I3C sensor interface specification that bundles 20 of the most commonly needed I3C features for developers and other standards organizations. The royalty-free specification includes backward compatibility with I2C, 12.5 MHz multi-drop bus that is over 12 times faster than I2C supports, in-band interrupts to allow slaves to not... » read more

What Makes A Chip Design Successful Today?
By Brian Bailey - 13 Dec, 2018 - Comments: 0

"Transistors are free" was the rallying cry of the semiconductor industry during the 1990s and early 2000s. That is no longer true. The end of Dennard scaling made the simultaneous use of all the transistors troublesome, but transistors remained effectively unlimited. This led to an era where large amounts of flexibility could be built into a chip. It didn't matter if all of it was being use... » read more

Efficient Low Power Verification & Debug Methodology Using Power-Aware Simulation
By Himanshu Bhatt - 13 Dec, 2018 - Comments: 1

By Himanshu Bhatt and Shreedhar Ramachandra Isolation, retention, and power switches are some of the important functionalities of power-aware designs that use some of the common low power techniques (e.g.) power shutoff, multi-voltage and advanced techniques (e.g.) DVFS, Low VDD standby, and biasing. The strategies for isolation, retention, and level shifter are specified in the power forma... » read more

Impacts Of Reliability On Power And Performance
By Ann Mutschler - 13 Dec, 2018 - Comments: 0

Making sure a complex system performs as planned, and providing proper access to memories, requires a series of delicate tradeoffs that often were ignored in the past. But with performance improvements increasingly tied to architectures and microarchitectures, rather than just scaling to the next node, approaches such as determinism and different kinds of caching increasingly are becoming criti... » read more

The Cost Of Accuracy
By Brian Bailey - 13 Dec, 2018 - Comments: 0

How accurate does a system need to be, and what are you willing to pay for that accuracy? There are many sources of inaccuracy throughout the development flow of electronic systems, most of which involve complex tradeoffs. Inaccuracy leaves an impact on your design in ways you are not even aware of, hidden by best practices or guard-banding. EDA tools also inject some inaccuracy. As the i... » read more

Making Sense Of DRAM
By Ed Sperling - 13 Dec, 2018 - Comments: 0

Graham Allan, senior manager for product marketing at Synopsys, examines the different types of DRAM, from GDDR to HBM, which markets they’re used in, and why there is such disparity between them. https://youtu.be/ynvcPfD2cZU     __________________________________ See more tech talk videos here. » read more

Softening Hardware: Using Application-Specific Processors to Optimize Modern SoC Designs
By Synopsys - 12 Dec, 2018 - Comments: 0

Over the past decade, the trend in SoC design has been to add more functionality into software, but moving functionality from hardware into software comes at a cost: software requires a processor, which, if not designed for optimal efficiency, could be slower and use more power than dedicated hardware. It often makes sense to implement smaller, specialized processors to tackle specific tasks wi... » read more

Blog Review: Dec. 12
By Jesse Allen - 12 Dec, 2018 - Comments: 0

Mentor's Harry Foster checks out how much time and effort is spent on verification of FPGAs and points to the increasing demand for verification engineers. Cadence's Paul McLellan digs into IC Insights' year-end report to see how some of the top semiconductor companies stack up. Synopsys' Taylor Armerding warns that air gaps, a valuable barrier against cyberattacks, are disappearing from ... » read more

Week In Review: Design, Low Power
By Jesse Allen - 07 Dec, 2018 - Comments: 0

RISC-V Western Digital announced big plans for RISC-V with a new open source RISC-V core, an open standard initiative for cache coherent memory over a network, and an open source RISC-V instruction set simulator. The SweRV Core features a 2-way superscalar design with a 32-bit, 9 stage pipeline core. It has clock speeds of up to 1.8Ghz on a 28mm CMOS process technology and will be used in vari... » read more

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