tag: Synopsys

Pain Points At 7nm
By Ed Sperling - 24 Mar, 2016 - Comments: 3

Early work has begun on 7nm. Process technology has progressed to the point where IP and tools are being qualified. There is still a long way to go. But as companies begin engaging with foundries on this process node—[getentity id="22586" comment="TSMC"] is talking publicly about it, but [getentity id="22846" e_name="Intel"], [getentity id="22819" comment="GlobalFoundries"] and [getentity ... » read more

An Unsustainable Divide
By Brian Bailey - 24 Mar, 2016 - Comments: 0

One of the great things about attending DVCon, or any other conference for that matter, is the networking. You get to see so many people who are eager to learn, to talk and to share ideas. When this happens, you tend to hear a lot of statements that have to rattle around in your mind for a while before you can start to make sense of them and see if any coherent themes emerge. By themes, I am... » read more

Prototype Like A Pro
By Tom De Schutter - 24 Mar, 2016 - Comments: 0

FPGA-based prototyping has been a key prototyping technique for many years. The steady increase in software content and thus the need to verify and validate the SoC in context of the software has resulted in an equally steady increase in its usage. FPGA-based prototyping or physical prototyping, as it is also called, offers a great way to develop software, verify the hardware in context of that... » read more

Are Simulation’s Days Numbered?
By Brian Bailey - 24 Mar, 2016 - Comments: 0

In the latest EDAC report, the value of IP surpassed the value of CAE tools for the first time. Verification tools are an important part of establishing confidence in IP blocks and simulation has been the mainstay of that IP verification strategy. But simulation is under increasing pressure, particularly for full-chip and SoC verification, because it has failed to scale. While it still remains ... » read more

How Do Design And Verification Change In The IoT Age?
By Frank Schirrmeister - 24 Mar, 2016 - Comments: 0

Where is the Internet of Things (IoT) on the hype curve? Are expectations too high, or is it really the next big thing? My recent trip to the Design Automation and Test Conference (DATE) in Dresden, Germany, did not give all the answers, but it definitely did shed some light for me on this topic. A very enthusiastic taxi driver took me back 25 years to the Nov. 9, 1989, the time when the Ber... » read more

Optimizing DDR Memory Subsystem Efficiency
By Synopsys - 23 Mar, 2016 - Comments: 0

This whitepaper applies virtual prototyping tools and best practice techniques to optimize the DDR memory subsystem configuration for a specific SoC application. Starting from a hypothetical Mobile Application Processor design, we will illustrate step-by step how to optimize: Address mapping Clock frequency Quality of Service (QoS) To read more, click here. » read more

Blog Review: March 23
By Jesse Allen - 23 Mar, 2016 - Comments: 0

How exactly does a giant fire behave in space? NASA plans to find out, in the latest top five tech picks from Ansys' Justin Nescott. Plus, never scrape ice off your car again and a pangolin-inspired motorcycle helmet. Cadence's Paul McLellan investigates the growing impact of dark silicon as Dennard scaling breaks down and the number of cores in a chip grows. Mentor's Harry Foster present... » read more

What’s Next for System-Level Power Modeling?
By Alan Gibbons - 23 Mar, 2016 - Comments: 1

Availability of models and libraries has long been one of the biggest barriers to the adoption of new EDA tools and methodologies, whether due to the investment needed to create these models and libraries or because of the “at-risk” nature of developing complex models in proprietary formats. With the approval of UPF3.0 (IEEE 1801-2015) this past December, we now have an industry standar... » read more

The Week In Review: Design/IoT
By Jesse Allen - 18 Mar, 2016 - Comments: 0

Tools Aldec updated its emulation and simulation acceleration software package for high speed prototyping boards, adding a SCE-MI Pipes-based flow for streaming large amounts of data, and a 30% speed increase for all emulation modes. Plus, Aldec's mixed-language FPGA design and simulation platform now includes a complete coverage analysis package for FPGA and ASIC designers with the addition... » read more

Blog Review: March 16
By Jesse Allen - 16 Mar, 2016 - Comments: 0

A bacterium that chows down on plastic could be a boon to reducing our huge piles of plastic waste, in this week's top five tech picks from Ansys' Bill Vandermark. Plus, silicon photonics got one step closer, keeping an eye on new neurons, and getting around with magnets. Can semiconductors be open sourced? Rambus' Aharon Etengoff considers what that would take, the potential impact on the I... » read more

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