tag: Synopsys

When Will 2.5D Cut Costs?
By Brian Bailey - 07 Aug, 2014 - Comments: 2

There is a constant drive to reduce costs within the semiconductor industry and, up until now, [getkc id="74" comment="Moore's Law"] provided an easy path to enable this. By adopting each smaller node, transistors were cheaper, but that is no longer the case, as explained in a recent article. The industry will need to find new technologies to make this happen and some people are looking towards... » read more

Making Software Better
By Ed Sperling - 07 Aug, 2014 - Comments: 0

Gauging the energy efficiency of software is a difficult task. There are many types of software, from embedded code all the way up to software that controls various modes of operation to downloaded applications. Some software interacts with other software, while other software works independently. And some works better on one SoC configuration than another, or on one iteration of an operating s... » read more

Changing The IP Supplier Paradigm
By Brian Bailey - 07 Aug, 2014 - Comments: 1

Just a few years ago, the [getkc id="43" comment="Intellectual Property"] (IP) business consisted of small blocks being sold by small companies and an almost over the wall delivery mechanism. The industry quickly realized the problems with this supply chain and the IP business went through very rapid change. At the same time, the average size of the IP blocks has increased and today, what we th... » read more

Power Reduction Techniques
By Mary Ann White - 07 Aug, 2014 - Comments: 0

As 16nm and 14nm finFET process nodes come into production toward the end of this year, the performance (up to 30% vs. 28nm planar CMOS), power (~30%) and area (up to ~50%) benefits have been well documented. The same can be said for the 28nm FD-SOI process as it gains more traction in the marketplace touting similar performance and power improvements as those for FinFET when compared against i... » read more

Established Nodes Getting New Attention
By Ed Sperling - 07 Aug, 2014 - Comments: 0

As the price of shrinking features increases below 28nm, there has been a corresponding push to create new designs at established nodes using everything from near-threshold computing to back biasing and mostly accurate analog sensors. The goals of power, performance and cost haven’t changed, but there is a growing realization among many chipmakers that the formula can be improved upon with... » read more

Test Becomes Power-Aware
By Ann Mutschler - 07 Aug, 2014 - Comments: 0

Power-aware test plans are changing, becoming far more extensive than the minimalist plans that were common just a few years ago. In the past would determine if they could power their design up, power it down, then they’d declare it done. “Sometimes they would find they could power it up and power it down once, but they couldn’t power it up a second time because they’d forgotten to ... » read more

Blog Review: Aug. 6
By Ed Sperling - 06 Aug, 2014 - Comments: 0

Mentor’s Colin Walls takes a look at bad behavior—the undefined kind that you get from doing C programming wrong and adding too much complexity up front. Cadence’s Brian Fuller interviews his colleague about what engineers need to know in regards to finFETs, advanced nodes and parasitic extraction. Short answer: Plenty. Synopsys’ Mick Posner is building FPGA prototype boards and... » read more

Leveraging Processor Extensibility To Build An Ultra Low-Power Embedded Subsystem
By Synopsys - 06 Aug, 2014 - Comments: 0

There is increasing demand for electronic devices to execute more functions while consuming less power and silicon area. To achieve this, systems instantiating multiple, heterogeneous processor cores optimized for low power and high performance are gaining popularity among design teams. In these systems, one or more deeply embedded processors execute a limited set of dedicated applications. The... » read more

Blog Review: July 30
By Ed Sperling - 30 Jul, 2014 - Comments: 0

Mentor’s Colin Walls looks at a free collaborative online tool called codepad, which can be used for compiling, interpreting and executing code quickly. Free is good—sometimes. Cadence’s Brian Fuller followed a recent panel on high-speed, cross-fabric interface design, which focused on why designers need to consider chip, package and board to ensure signal and power integrity. So what... » read more

IP Integration Challenges Rising
By Ann Mutschler - 24 Jul, 2014 - Comments: 0

It’s not just [getkc id="80" comment="lithography"] that is putting a crimp in sub-28nm designs. As more functions, features, transistors and software are added onto chips, the pressure to get chips out the door has forced chipmakers to lean more heavily on third-party IP providers. Results, as you might expect, have been mixed. The number of blocks has mushroomed, creating its own web of ... » read more

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