tag: Synopsys

Experts At The Table: Power Budgeting
By Ed Sperling - 03 Jun, 2013 - Comments: 0

By Ed Sperling Low-Power Engineering sat down with Barry Pangrle, solutions architect for low-power design and verification at Mentor Graphics; Cary Chin, director of technical marketing for low-power solutions at Synopsys; Vic Kulkarni, general manager of the RTL business unit at Apache Design Solutions; Matt Klein, principal engineer for power and broadcast applications at Xilinx; and Paul ... » read more

The Week In Review: May 31
By Ed Sperling - 31 May, 2013 - Comments: 0

By Ed Sperling Mentor Graphics and GlobalFoundries teamed up to deliver 20nm design kits that include Mentor’s place and route tool, including verification and conflict resolution engines for double-patterning violations. The 20nm process is used for GlobalFoundries’ 14nm finFETs. Mentor also received 16nm finFET certification from TSMC for the same tools plus its physical verification pl... » read more

Experts At The Table: The Growing Signoff Headache
By Ed Sperling - 31 May, 2013 - Comments: 0

By Ed Sperling Low-Power/High-Performance Engineering sat down to discuss signoff issues with Rob Aitken, an ARM fellow; Sumbal Rafiq, director of engineering at Applied Micro; Ruben Molina, product marketing director for timing signoff at Cadence; Carey Robertson, director of product marketing for Calibre extraction at Mentor Graphics; and Robert Hoogenstryd, director of marketing for design... » read more

Formal Verification Comes Of Age
By Ed Sperling - 30 May, 2013 - Comments: 0

By Ann Steffora Mutschler Formal verification technology, also known as formal property checking, has been in existence since the early 1990s. Still, it’s only in the past five years that it has made big strides in the last five years in terms of the capacity of the technology to handle bigger pieces of a design, leveraging advancements in computing as well as improvements to the algor... » read more

The X Factor
By Ed Sperling - 30 May, 2013 - Comments: 0

By Ed Sperling The number of unknowns is growing in every segment of SoC design all the way through manufacturing, raising the stakes between reliability and the tradeoffs necessary to meet market windows. Tools are available to deal with some of these unknowns, or X’s, but certainly not all of them. Moreover, no single tool can handle all unknowns, some of which can build upon other unkn... » read more

Pitfalls In Subsystem Reuse
By Ann Mutschler - 30 May, 2013 - Comments: 0

By Ann Steffora Mutschler IP subsystems provide a ‘divide and conquer’ approach to SoC design by combining multiple IP blocks together to perform individual functions such as audio, graphics or video. The advantage of this approach is that these functions can be tested and verified at the unit level then integrated with the top-level SoC. This also facilitates reuse because each of ... » read more

Software, From Zero To Hero
By Tom De Schutter - 30 May, 2013 - Comments: 0

By Tom De Schutter As the amount of software in electronics applications continues to grow across many markets, from mobile phones to automotive hybrid systems, it is interesting to see how people portray this new-found dependency on software availability. I recently saw a presentation slide with the title: software delays products. Well, that’s one way of looking at it, but it’s a rather ... » read more

FinFET Technology
By Various Writers - 30 May, 2013 - Comments: 0

This white paper discusses the major challenges with FinFETs and how TSMC has been collaborating with Synopsys, one of their ecosystem partners, to deliver a complete solution. Key elements of this solution include comprehensive FinFET profiling without impact to design tool runtime and proven, verified IP availability. The TSMC 16-nm FinFET solution will ensure mutual customers swiftly move to... » read more

3D Brings Test Into Fashion
By Ann Mutschler - 16 May, 2013 - Comments: 0

By Ann Steffora Mutschler As integral and critical as test is to the success of an SoC, it isn’t always one of those topics in semiconductor design that seems fashionable. But as Bassilios Petrakis, director of product marketing for test products at Cadence pointed out, “[Test] is not in fashion, but when we hit one of those brick walls then suddenly we have to think how we are going to... » read more

Cost vs. Value
By Ann Mutschler - 10 May, 2013 - Comments: 0

By Ann Steffora Mutschler The increasing amount of mixed-signal content being included in SoCs for automotive, networking and all manner of mobile devices is reinvigorating the mixed-signal industry. While this is great news for companies playing in anything related to mixed-signal technology, it also means increasing complexity for the engineering teams pulling all the pieces together. “... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2026 SMG   |  Terms of Service  |  Privacy Policy