tag: Synopsys

Raising The Stakes For IP
By Ed Sperling - 14 Feb, 2013 - Comments: 0

By Ed Sperling As the amount of IP in an SoC increases, so do the number of players who want to strengthen their position in this market. The big acquisitions that began several years ago over time have proved to be just opening salvos—something that was impossible to predict when this shift began. Synopsys’ purchase of Virage Logic and Cadence’s purchase of Denali, both of which occu... » read more

Too Hot To Handle
By Ed Sperling - 14 Feb, 2013 - Comments: 0

By Ann Steffora Mutschler It used to be that a device could be designed to a thermal design power. The worst case power scenario would be imagined, and the device would be designed with that in mind. But those good old days are gone. Especially for consumer devices, how a device is going to behave with respect to time, or how people are going to use it, must be understood as completely a... » read more

Managing Electrical Communications Better
By Ann Mutschler - 14 Feb, 2013 - Comments: 0

By Ann Steffora Mutschler Managing the electrical components of signal paths between IC, package, board and system is no small task, and it’s only growing in complexity. Understanding how to correctly optimize the communications within a system is critical given that the I/O power is becoming a significant portion of the overall chip power as the number of bits and the speed at which t... » read more

New Issues In Signoff
By Ed Sperling - 14 Feb, 2013 - Comments: 0

By Ed Sperling Signoff has always been a challenge at every stage of an SoC design flow. No matter how good a design looks, or how well a prototype works, there are still problems that can crop up at any stage of the design flow all the way into manufacturing that can leave engineering teams shaking their heads. Even at mainstream process nodes, respins are common. At advanced nodes—part... » read more

Big Rocks First
By Synopsys - 14 Feb, 2013 - Comments: 0

By Cary Chin Up on the wall in the hallway by the printer at my office, there’s an article by a management consultant entitled, “PUT THE BIG ROCKS IN FIRST!” It describes the demonstration that has been conducted and described many times by many consultants and motivational speakers over the years. Starting with an empty bucket, place large rocks in the bucket until it is full. Repeat by... » read more

Experts At The Table: Low-Power Verification
By Ed Sperling - 09 Feb, 2013 - Comments: 0

Low-Power Engineering sat down to discuss the problems of identifying and verifying power issues with Barry Pangrle, solutions architect for low-power design at Mentor Graphics; Krishna Balachandran, director of low-power verification marketing at Synopsys; Kalar Rajendiran, senior director of marketing at eSilicon; Will Ruby, senior director of technical sales and support at Apache Design; and... » read more

SoC Architects Face Big Challenges
By Ed Sperling - 31 Jan, 2013 - Comments: 0

By Ann Steffora Mutschler While the geometries of advanced node processes such as 28nm and below may not greatly impact SoC architectures, the complexity enabled by the leading edge brings intense challenges all the same. With the ability to put more transistors onto a chip come new possibilities such as the increasing use of multi-core architectures and lots of integrated hardware en... » read more

Mixing It Up
By Ed Sperling - 31 Jan, 2013 - Comments: 0

By Ann Steffora Mutschler To enable the next level of productivity in the verification space, certain tools need to be combined and integrated in a very meaningful way. The concept is far from new. This happened on the RTL to GDS front between synthesis and place and route. The tools work very closely and there is bi-directional collaboration. It also happened in the functional verification... » read more

Cost Per Transistor Gets Fuzzier
By Ed Sperling - 31 Jan, 2013 - Comments: 0

By Ed Sperling Cost per transistor always has been a major reason for chipmakers to migrate to the next process node. By shrinking transistors and adding more logic, performance usually gets a boost. Moreover, that usually provides enough engineering wiggle room to add some improvements in energy efficiency. The basic assumption that you can double the number of transistors every 24 months,... » read more

Hybrid Prototype Benefits
By Nithya Ruff - 31 Jan, 2013 - Comments: 0

By Troy Scott This month Nithya asked me to contribute a post on hybrid prototyping and add some color to how design teams have been benefiting from integration between virtual and FPGA-based prototypes. It’s been about six months since Synopsys announced the availability of a data exchange, which links a Virtualizer Development Kit (VDK) to the HAPS FPGA-based prototyping system based on AM... » read more

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