Chip Industry’s Technical Paper Roundup: Oct 25


New technical papers added to Semiconductor Engineering’s library this week. [table id=59 /] » read more

On-chip 2D/3D Photonics Integration Solution Using Deposited Polycrystalline Silicon for Optical Interconnects Applications


A new technical paper titled "Polycrystalline silicon PhC cavities for CMOS on-chip integration" was published by researchers at Tyndall National Institute, Munster Technological University, and Université Grenoble Alpes, CEA, LETI. "In this work, we present an on-chip 2D and 3D photonics integration solution compatible with Front End of Line integration (FEOL) using deposited polycrystalli... » read more

Manufacturing Bits: Sept. 12


Failure analysis for 2.5D/3D chips Imec has developed a new failure analysis method to localize interconnection failures in 2.5D/3D stack die with through-silicon vias (TSVs). This technique is called LICA, which stands for light-induced capacitance alteration. It addresses the reliability issues for 2.5D/3D devices in a non-destructive and cost-effective manner at the wafer level. For s... » read more

Manufacturing Bits: March 8


5G mmWave consortium Amid a slowdown in the cell phone business, the market is heating up for perhaps the next big thing in wireless—5th generation mobile networks or 5G. Carriers, chipmakers and telecom equipment vendors are all rushing to get a piece of the action in 5G, which is the follow-on to the current wireless standard known as 4G or long-term evolution (LTE). Radio-frequency (RF... » read more

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