Signoff Of Synthesis-Optimized Registers


How do you know when you sign off on a complex chip design that everything is going to work? There are more variables, more elements that need to be verified, and more waivers that need to be generated. Suresh Barla, senior director of field applications at Synopsys, talks about how to ensure that RTL is fully optimized for PPA targets in large designs that can include hundreds of millions of g... » read more

So Many Waivers Hiding Issues


Semiconductor Engineering sat down to discuss problems associated with domain crossings with Alex Gnusin, design verification technologist for Aldec; Pete Hardee, director, product management for Cadence; Joe Hupcey, product manager and verification product technologist for Mentor, a Siemens Business; Sven Beyer, product manager design verification for OneSpin; and Godwin Maben, applications en... » read more

Pattern Matching in Design and Verification


Pattern matching (PM) was first introduced as the semiconductor industry began to shift from simple one-dimensional rule checks to the two-dimensional checks required by sub-resolution lithography. These rule checks proved far more complex to write, hard to code for fast runtimes, and difficult to debug. Incorporating an automated visual capture and compare process enabled designers to define t... » read more