VLSI 2026: Intel 18A Platform Momentum From Devices To Routed Designs

Intel Foundry’s process technology roadmap is powered by innovations that are enabling customers to build increasingly capable products for the artificial intelligence (AI) era. At the 2026 IEEE/JSAP Symposium on VLSI Technology & Circuits, Intel Foundry presented progress on a number of important aspects of our front-end silicon process innovations. This includes Intel 18A-P featuring Power Boost, our first performance enhancement to the Intel 18A node family, now in risk production. We also share research on the advantages of backside power, supported by data from designers on the product side of Intel on how building products on a backside power/gate-all-around (GAA) process provides multiple advantages.

Among the six research papers presented at the event, we demonstrated our continued advancement of gallium nitride (GaN) technology by sharing new developments in efficient power management of scalable digital logic on a 300 mm GaN and silicon platform. In addition, we presented a scaled complementary FET (CFET) process with features to balance performance benefit and process risk as well as subtractive ruthenium (sRu) interconnects with airgap, enabling a more efficient metallization scheme for tight pitches. Intel Foundry’s continued investment in R&D underscores our commitment to our customers, delivering silicon-validated innovations that enable future-ready performance and efficiency gains.

CPU Learnings with GAA Transistors and Backside Power

Today, the industry’s biggest power delivery challenges are structural. Frontside power delivery networks no longer scale to support increasingly demanding workloads, leading to vanishing voltage margins and tighter thermal and reliability constraints. Backside-powered GAA nodes offer a scaling solution for next generation CPUs, AI accelerators, and system of chips (SoCs).

Research by Intel engineers on CPU cores using GAA with backside power found that lower IR drop across the power delivery network allows more transistor performance to translate into real core frequency and closer-to-ideal silicon scaling. At low operating voltages around 0.5 V, GAA designs with backside power demonstrated approximately 30% higher frequency versus FinFET.¹ This enables new low-voltage operating points that were previously impractical for mobile, AI edge, and energy-efficient compute. These gains are especially relevant for power-constrained workloads, where reducing voltage delivers more power savings with longer battery life, and lower cooling and packaging costs.

Figure 1. Core frequency improves by approximately 30% at 0.5 V for GAA backside power design.

Backside Power Delivery Impact on Routed Designs

At VLSI 2026, Intel Foundry engineers shared improvements in backside power delivery on advanced nodes. Backside power delivery shifts major power routing to the rear of the wafer, reducing congestion by freeing frontside interconnect for signals. Routed blocks showed approximately 11% area reduction,² which improved routing completion using fewer vias and shorter wires.

To mitigate IR-drop challenges, Intel 18A demonstrated peak dynamic voltage droop under 10 mV versus more than 90 mV on Intel 3 with its frontside power delivery network. This 10x dynamic droop reduction enables a 5-6% frequency uplift or up to 15% power reduction versus comparable frontside interconnect technology.² Delivering power more directly with lower resistance enables stable voltage under switching, reducing timing guardbands.

As backside power removes power wiring from the lowest frontside metals, those layers no longer need extremely tight spacing. This allows customers to use more cost effective 32 nm metal processes on Intel 18A and Intel 18A-P, which require fewer masks and manufacturing steps. In addition, Intel 18A showed improved clock distribution, more compact memory layouts, and better alignment with future 3D and vertically stacked architectures.

Intel 18A‑P: The Next Step in Intel 18A Platform Evolution

Intel 18A-P builds on the same GAA and backside power foundation while remaining design-rule compatible with Intel 18A. This enables customers to gain performance benefits without redesigning entire layouts or libraries. Based on research by our engineers, the gains from Intel 18A-P CMOS technology enhancementscome from added device options, tighter variation control, improved contacts, interconnect refinements, and design-technology co-optimization.

As shown in Figure 2, fully routed block results demonstrated 9% iso-power performance gain at 0.75 V on a standard ARM core sub-block, translating to 18% lower power at the same performance compared to Intel 18A.³ These silicon-validated low-voltage gains support energy-efficient designs for AI, high-performance computing (HPC), and emerging compute applications.

Figure 2. Intel 18A-P demonstrates 9% iso-power performance gain at 0.75 V compared to Intel 18A on an industry standard ARM core sub-block.

Intel 18A‑P also introduces material innovations that deliver 20-40% improvement in thermal resistance of the overall stack³ when combined with enhanced electronic design automation (EDA) workflows, building on earlier improvements introduced with Intel 18A.

Figure 3. In the Power Boost dual contact architecture, the front side contact and the direct backside contact are connected to PowerVia.

Intel 18A-P also features Power Boost, the industry’s first implementation of a novel dual contact architecture. Enabled by PowerVia backside power delivery, low-resistance frontside and direct backside contacts show improved resistance for both NMOS and PMOS transistors compared to Intel 18A. Intel 18A-P enables enhanced performance at matched footprint for power-constrained applications including mobile, AI accelerators, and data centers.

Additional Significant Breakthrough Research

Efficient power management logic using 300 mm GaN and silicon technology: Following up on Intel Foundry’s recent achievement of creating the world’s thinnest GaN chiplet, our engineers presented another breakthrough innovation at VLSI 2026. Together with collaborators from the University of California, San Diego, the team proved it’s practical to build efficient multi-thousand-gate digital control circuits directly on one chip by using a hybrid GaN nMOS and silicon pMOS approach in a 300 mm manufacturing process. The team achieved a record power-delay product (PDP) of just 6.2 attojoules (aJ) per stage — over 1,000x more efficient than prior GaN logic approaches, and showcased the largest-scale integrated logic on GaN to date.⁴ This future technology will enable on-chip control integration by reducing cost, size, and complexity while improving system performance.

CFET integration at 45 nm gate pitch on a 2×2 ribbon stack: CFET 3D transistors combine NMOS and PMOS transistors stacked vertically for more performance in a smaller space. Our team built working logic circuits at a very small size (45 nm pitch), along with advanced integration features including backside power delivery, direct backside contacts, and novel epi‑epi vias as a compact vertical connection. We demonstrated a bonding technique for performance improvement without introducing parasitic penalties. In addition, we showed how device depopulation enables a common gate architecture by selectively removing unused devices within a CFET stack to reduce process complexity and improve design flexibility.

Performance improvement from subtractive Ru interconnects with airgap: Our team demonstrated a next‑generation interconnects approach featuring subtractive Ru wiring with airgap, marking the first integration of this metallization scheme with functional RibbonFET devices on a test chip. At matched leakage, it achieves roughly a 2% improvement in circuit performance as compared to conventional copper interconnects, driven by a capacitance reduction of up to 35% from the airgap. The research also shows up to 50% reduction in lower and upper via resistance, thereby improving vertical connections.⁵ Together, these results deliver faster and more efficient signal transmission, and provide a scalable path for improving the performance of interconnects at tight pitches.

From Innovation to Execution: What’s Next for Intel 18A

At VLSI 2026, we demonstrated that Intel 18A platform progress is moving from theory to execution, supported by silicon data and routed benchmarks. Together, GAA transistors, backside power, and the Intel 18A‑P extension show sustained forward momentum across performance, power efficiency, and design enablement. For our customers, these continued advancements ensure a production-ready platform that accelerates time-to-market for next-generation designs.

Endnotes

1. “CPU Cores in GAA with Backside Power: Silicon-Validated Design Insights,” IEEE/JSAP Symposium on VLSI Technology & Circuits, June 2026.
2. “Backside Power: Enabling Energy Efficient Performance on Advanced Node Designs,” IEEE/JSAP Symposium on VLSI Technology & Circuits, June 2026.
3. “Intel 18A-P CMOS Technology Enhancement Featuring Advanced RibbonFET (GAA) Transistors and PowerVia for High-Performance Computing,” IEEE/JSAP Symposium on VLSI Technology & Circuits, June 2026.
4. “A 300 mm Monolithic GaN MOSHEMT and Si pMOS Technology Demonstrating Energy-Efficient Multi-Thousand-Gate Digital Logic for Power Management,” IEEE/JSAP Symposium on VLSI Technology & Circuits, June 2026.
5. “Performance Improvement from Subtractive Ruthenium Interconnects with Airgap,” IEEE/JSAP Symposium on VLSI Technology & Circuits, June 2026.