Where the pitfalls are in advanced-node designs and multi-chip packages, and best practices for managing them.
Companies can benefit from advancements in the latest semiconductor process technology by delivering smaller, faster and lower power products, especially for those servicing mobile, high performance computing and automotive ADAS applications. By using 7nm processes, design teams are able to add a lot more functionality onto a single chip and lower the power consumption by scaling operating voltage down to 500mV without sacrificing performance. However, the risk of design failure and its associated cost at this advanced node is significantly higher than ever before.
While supply voltage can be as low as 500mV, threshold voltage does not scale accordingly, resulting in much tighter noise margin and smaller window for acceptable voltage drop. Higher levels of integration can result in increased current density, as well as more power density variations across the chip. This, along with increase in metal resistance, makes meeting reliability requirements such as electromigration (EM) and electrostatic discharge (ESD) a major design challenge. The localized self-heat effects of finFETs further exacerbate the thermal impact on the chip’s performance and reliability. Furthermore, the use of 2.5D/3D stacked die and InFO packaging creates additional design complexity.
Accurately model chip, package and PCB
Chips today include high-performance, low-power digital logic, high-speed DDR and SerDes, analog IPs, RF IPs and mixed-signal blocks, sitting on an advanced 2.5D/3D package or even directly on wafer-level packaging. The power delivery network (PDN) globally affects the chip, package and the PCB, and therefore cannot be analyzed by traditional methods of divide-and-conquer without sacrificing accuracy. These seemingly disparate domains need to be simultaneously simulated to gain insights on chips’ true performance and behavior.
Complex IP such as SerDes, PLL, TCAM and other macros need detailed temporally accurate and spatially accurate models that capture their electrical behavior over multiple different dimensions. Even the modeling of foundation IPs, such as standard cells and memories, has to be sufficiently detailed to capture their electrical states with pico-second accuracy (switching current, capacitance) to predict the voltage drop of the combined chip, package and PCB system for sign-off confidence. This is especially true for multi-height cells. Transistor-level SPICE simulations over a wide range of supply voltage conditions is needed to make these models relevant and accurate for 7nm SoC power noise analysis. Additionally, not only do you need a model of the package that has per-bump resolution to accurately reflect the spatial distribution of switching current, you also should consider incorporating a model of the PCB in the analyses.
Simulate multi-target interactions
In addition, the traditional silo-based design approach focuses on single task sign-off without data sharing between multiple design targets. Even with sufficient margining, the limited visibility of this approach can produce erroneous results and increase the risk of design failure. Instead, simulation needs to capture interaction between multiple targets. For example, looking at power and timing together can help you make better power-versus-performance tradeoffs and meet your designs’ performance goals. Or understanding how increasing current density as well as higher temperature impacts EM can help you improve your design, not only to meet the signoff requirements, but also to ensure that your chip reliably operates during it’s expected lifetime.
Reliability is one of the major concerns for advanced node FinFET designs. There are close interactions between power, temperature, EM and ESD that need to be accurately modeled and simulated to ensure the reliability of your design. These interactions also need to be analyzed within the context of the latest packaging technologies.
Thermal impact on EM and ESD
Chip-package temperature can have a significant impact on the chips’ overall performance and reliability. Designs at 7nm enable higher levels of integration, which in turn increases current density and raises the overall ambient temperature of the chip and package. This increase in temperature can lower the devices’ performance and accelerate EM failures. In addition, finFET devices result in localized self-heat, adding another layer of challenge for interconnect reliability. To increase confidence in your design, you need to thoroughly analyze the thermal impact on device and interconnect reliability.
Higher interconnect resistance and current density coupled with larger thermal variation increase the risk of EM failure. It is important to determine the EM violations on interconnects, but it also is valuable to understand the probability of a failure of a given block, IP or chip over the lifetime of the product. Statistical EM budgeting using FIT (failure in time) based approaches can provide better visibility into the overall reliability of the design. This, along with temperature-aware EM analysis, provides comprehensive lifetime validation.
Designing robust ESD protection is a real challenge at a smaller process node. Design teams are no longer able to reuse the scheme from older nodes as the ESD design window continues to shrink. At the same time, the ESD guard ring becomes thinner, risking the robustness of the protection. Use of stacked or multi-die packaging further exacerbates the issue by adding complexity to the I/O protection scheme. To accurately analyze all possible ESD failure scenarios requires package-aware chip-level simulation.
Advanced package handling
The latest wafer level packaging technologies, such as TSMC’s InFO, can help reduce power and temperature across the die, as well the thickness of the package, but it also is significantly more complex. The interconnects for these packages are not always planar and can have irregular structures, which requires special handling for accurate RLC extraction and EM rules. In addition, extracting these geometries need to consider interactions between package and die metal layers for accuracy.
Thermal-aware mechanical stress is another reliability issue that needs to be modeled for InFO type packages.
Effects of mixed-signal noise coupling
Mixed-signal ICs, especially those that contain RF, analog and digital cores, are highly sensitive to shared substrate noise. Analog and RF circuits are especially prone to noise issues conducted through the substrate. High-speed digital circuits that inject noise at certain harmonics can cause havoc on RF performance of such ICs. Design teams need to accurately model and analyze the coupling of substrate noise to ensure the robustness of their chips.
Rely on proven sign-off flow
With extremely tight noise margin for 7nm devices, it is essential to not underestimate the value of industry proven multi-physics sign-off flows. It is important to make sure that your extraction, modeling and simulation tools are foundry-certified for accuracy with thousands of tape-out successes, backed by the largest team of power experts.
First-time silicon success is becoming increasingly difficult to achieve with traditional analysis methodologies. To deliver highly integrated and reliable products expected by today’s market, it is more critical than ever to make sure that your verification methodology has the broadest coverage with the highest level of accuracy and predictability in the most efficient manner.