Libraries: Standardization and Requirements For Power-Aware Dynamic Simulation


INTRODUCTION Multivoltage (MV) based power-aware (PA) design verification and implementation methodologies requires special power management attributes in libraries for standard, MV and Macro cells for two distinctive reason. The first aspect is to provide power and ground (also bias) supply or PG-pin information, which is mandatory for PA verification. The second reason is to provide a distin... » read more

Calibre Evolves Constantly


I find it truly amazing that despite the constantly changing tide in the digital IC design industry that some tools have remained in that number 1 spot for over a decade. The three tools that immediately come to mind are Synopsys’ PrimeTime and Design Compiler and Mentor’s Calibre. I remember back when I first started covering the industry in the mid-1990s that Quad Design’s Motive sta... » read more

Working With Custom Checkers In Dynamic Simulation Of Low Power Designs


Power-aware simulators can provide a wide range of automated assertions in the form of dynamic sequence checkers that cover every possible PA dynamic verification scenario. However, design specific PA verification complexities may arise from adoption of one or a multiple of power dissipation reduction techniques, from a multitude of design features — like UPF strategies — as well as from ta... » read more

Correlating Software Execution With Switching Activity To Save Power In SoC Designs


There is probably no more pointless waste of energy than lighting and heating a room that is empty. The obvious optimization: notice that no one is there and turn off the lights. It works the same on an SoC or embedded system. To save energy, system developers are adding the ability turn off the parts of the system that are not being used. Big energy savings but with no compromise to functional... » read more

Finding The Unexpected In High Performance Designs


It was growing dark as I drove a winding road on Mt. Hood, deep in the American northwest forest. The firs were thick, creating a lot of shadows and making it tough to see things clearly. Then out of the corner of my eye, I swear I saw a 10-foot “man” covered with brown fur. It looked a lot like a Wookie. But everyone knows Wookies aren’t real. It had to be Bigfoot! I slammed on th... » read more

Finding Evasive System-Level Bugs Using Memory Consistency Algorithm


Over Easter weekend in 2015 there was a jewelry heist at the safe deposit building at Hatton Gardens in London. The safe deposit vault was in the basement of a building and is used by jewelers in the area for storing large amounts of diamonds, jewelry, precious metals, and cash. The thieves made off with over $300 million in loot, making it the biggest heist in British history. For a while it l... » read more

Five Pitfalls In PCIe-Based NVMe Controller Verification


Non-Volatile Memory Express (NVMe) is gaining rapidly in mindshare among consumers and vendors. Some industry analysts are forecasting that PCIe-based NVMe will become the dominant storage interface over the next few years. With its high-performance and low-latency characteristics, and its availability for virtually all platforms, NVMe is a game changer. For the first time, storage devices and ... » read more

Need Emulation Now? You’ve Got It


Did you know that the way companies use hardware emulation has changed? Until recently, companies had no choice but to house their emulators in a lab and hard wire them (using lots of wires) to other supporting hardware and workstations dedicated to a single project at a time. The emulator and its set up was accessible to users at only that location and switching between projects was difficu... » read more

Deterministic ICE App Tackles ICE Limitations


Historically, SoC verification has used In-Circuit Emulation (ICE) to exercise the design under test (DUT) by connecting physical targets to an emulator. ICE delivers the advantage of being able to run real-world usage scenarios before tape-out. However, an ICE-based verification environment is hampered by several inherent limitations. It is restricted to trigger- and waveform-based debug. W... » read more

The 2016 Wilson Research Group Functional Verification Study


I am writing a series of blogs that presents the findings from our new 2016 Wilson Research Group Functional Verification Study. Similar to my previous 2014 Wilson Research Group functional verification study blogs, I plan to begin this set of blogs with an exclusive focus on FPGA trends. Why? For the following reasons: Some of the more interesting trends in our 2016 study are related to F... » read more

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