Co-Modeling Takes Emulation To The Next Level: System-Of-Systems


As designs move beyond System-on-Chip (SoC) to more complex System-of-Systems (SoS), it’s essential for design teams to effectively verify that these systems function together as intended. Increasingly, system design companies are turning to emulators as the only verification platform with the capacity and performance to validate that their SoC and SoS designs function as intended. Todayâ€... » read more

An Incremental Approach To Reusing Automated Tests From IPs To SoCs


Over the past few years, lots of energy has been invested in improving the productivity and quality-of-results of design verification. A promising effort toward this end is that both commercial and in-house tools have been developed to improve the productivity and efficiency of verification at the block, subsystem, and system levels. These tools raise the level of abstraction, increase test-gen... » read more

Body Bias: What It Is, And Why You Should Care


In case you hadn’t noticed, the use of integrated circuits (ICs) has exploded over the past decade. From the cheapest novelty toy to automobiles to implanted medical devices, it seems like everything we touch has an electronic component in it somewhere. Not surprisingly, that growth has brought with it a vastly expanded number and variety of IC design requirements that design companies must s... » read more

How Virtual Emulation Gives The Storage Market A Leg Up


By Ben Whitehead and Paul Morrison The storage market demands that huge amounts of data and information be stored securely and be accessible anywhere and anytime, driving the adoption of key technologies and use models. According to GSMAintelligence.com, newly created digital data is doubling every two years. This means increasing amounts of storage must be available at the same pace. A... » read more

UPF Power Domains And Boundaries


The Universal Power Format (UPF) plays a central role in mitigating dynamic and static power in the battle for low-power in advanced process technology. A higher process node is definitely attractive as more functionality integration is possible in a smaller die area at a lower cost. However, in reality, this comes at the cost of exponentially increasing leakage power. This is because the minim... » read more

Estimating Power And Performing Optimization


Power analysis and optimization have gained importance over the last few years. During this time it has become obvious how critical it is to use realistic payloads to accurately estimate power and perform optimization tasks. Designers have a range of different objectives and concerns when it comes to power. On one side, a team wants to ensure that the average power of their chip is low enough t... » read more

Libraries: Standardization and Requirements For Power-Aware Dynamic Simulation


INTRODUCTION Multivoltage (MV) based power-aware (PA) design verification and implementation methodologies requires special power management attributes in libraries for standard, MV and Macro cells for two distinctive reason. The first aspect is to provide power and ground (also bias) supply or PG-pin information, which is mandatory for PA verification. The second reason is to provide a distin... » read more

Calibre Evolves Constantly


I find it truly amazing that despite the constantly changing tide in the digital IC design industry that some tools have remained in that number 1 spot for over a decade. The three tools that immediately come to mind are Synopsys’ PrimeTime and Design Compiler and Mentor’s Calibre. I remember back when I first started covering the industry in the mid-1990s that Quad Design’s Motive sta... » read more

Working With Custom Checkers In Dynamic Simulation Of Low Power Designs


Power-aware simulators can provide a wide range of automated assertions in the form of dynamic sequence checkers that cover every possible PA dynamic verification scenario. However, design specific PA verification complexities may arise from adoption of one or a multiple of power dissipation reduction techniques, from a multitude of design features — like UPF strategies — as well as from ta... » read more

Correlating Software Execution With Switching Activity To Save Power In SoC Designs


There is probably no more pointless waste of energy than lighting and heating a room that is empty. The obvious optimization: notice that no one is there and turn off the lights. It works the same on an SoC or embedded system. To save energy, system developers are adding the ability turn off the parts of the system that are not being used. Big energy savings but with no compromise to functional... » read more

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