Deterministic ICE App Tackles ICE Limitations

Historically, SoC verification has used In-Circuit Emulation (ICE) to exercise the design under test (DUT) by connecting physical targets to an emulator. ICE delivers the advantage of being able to run real-world usage scenarios before tape-out. However, an ICE-based verification environment is hampered by several inherent limitations. It is restricted to trigger- and waveform-based debug. W... » read more

The 2016 Wilson Research Group Functional Verification Study

I am writing a series of blogs that presents the findings from our new 2016 Wilson Research Group Functional Verification Study. Similar to my previous 2014 Wilson Research Group functional verification study blogs, I plan to begin this set of blogs with an exclusive focus on FPGA trends. Why? For the following reasons: Some of the more interesting trends in our 2016 study are related to F... » read more

Optimizing Emulator Utilization

The growing pressures of market schedules, design complexity and the ever-increasing amount of embedded software in today’s SoCs has put verification in the hot-seat. Now that new emulation tools can link hardware and software verification, SoC designers are turning to emulation more than ever before to debug embedded software. The standard method for debugging software with an emulator is wi... » read more

Addressing The Challenges Of Automotive Motor Control

By Andrew Talan and Ahmed Eisawy As you leave work today and enter the parking lot, you hit the unlock button on your car remote. Using the power lift to open the hatch back, you put your laptop bag in the back of the car. While seated in the car, you adjust your seat position and bump your driver-side mirror into a new position and then head for home. You probably don’t think much about y... » read more

The Secret to Reaching Rapid Verification Closure

Every design team is looking to reduce RTL verification time in order to meet aggressive schedules. Successful teams have moved their level of design abstraction up to the C++ or [gettech id="31018" comment="SystemC"] level and employ [getkc id="105" comment="high-level synthesis"] (HLS) within their design flow. By taking advantage of this high-level description, these teams also plug into int... » read more

Save Power And Area By Eliminating Redundant Resets

Resets initialize hardware by forcing it into a known state, either on design start up or to recover from an error. In today’s SoC designs, it is not uncommon to see designs with millions of registers that have resets. Unfortunately, many of these resets are redundant. Leaving these unnecessary register resets in the design leads to increased power consumption, excess area, and routing conges... » read more

An Introduction To Reducing Dynamic Power

In the past few blogs we have been primarily talking about UPF and applying the Successive Refinement process to save power. But, this process addresses leakage power. In this session we want to talk about how to save dynamic power. As designs move to finFET technology, dynamic power is the dominant contributor to power consumption. Power consumption trend. I recently sat down with my c... » read more

Power Analysis Plus Power Management

In my earlier blogs we've heard from some of the experts on using UPF in the successive refinement flow. We’ve talked about controlling leakage power, bringing power down, and validating power management behavior using coverage and simulation, including debug and clock domain crossing verification. In order to do the last step in the successive refinement flow, you need to use emulation be... » read more

Automating Coverage And Analysis Of Low Power Designs

There are some exciting new things in the just released IEEE1801-2015 (aka UPF 3.0), some of which have significant benefits for coverage of low power designs, which is what we’ll be looking at in this blog. One of these is improved semantics for the add power state command, introduced in IEEE1801-2009 (aka UPF 2.0). These clarifications to the add power state command allow you to clearly ... » read more

Micro-Architectural Exploration for Low Power Design

In the first part of this series, we had discussed the need to perform power optimizations and exploration at higher levels of abstractions where the potential to reduce the power consumption is highest. We presented the need for making coarser changes at higher level of abstractions to exploit full power saving potential. In the second part, we discussed some very potent micro-architectural te... » read more

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