The big question is whether it will work, and there’s no clear answer yet. But without EUV, the costs and challenges could skyrocket.
It’s too early to make that determination right now, but there are more uncertainties than ever for the oft-delayed technology. Originally aimed for the 65nm node in the late 1990s, EUV has missed a number of insertion windows despite strong industry support and billions of dollars spent on the technology.
As of now, EUV remains delayed and will miss the 10nm node. Chipmakers are targeting EUV for 7nm, although the technology could get pushed out to 5nm. As before, there are still issues with the EUV source, mask infrastructure and resists.
In any case, the big and real test for EUV is just getting underway. Late last year, ASML shipped its first production-worthy EUV scanner. The 13.5nm wavelength tool, dubbed the NXE:3300B, has a numerical aperture of 0.33 and a resolution of 22nm half-pitch.
At the recent SPIE Advanced Lithography symposium in February, TSMC originally hoped to present the first results of the NXE:3300B in operation. But at SPIE, TSMC officials said the tool went down due to a “laser misalignment” issue. Then, ASML said the issue was resolved and the tool was running during the same week.
The event was a mere hiccup in the big scheme of things. The bigger issue was not “laser misalignment,” but rather TSMC and others presented little or no critical data on the real performance of the NXE:3300B in action, as they had hoped. There were few details on process capabilities, throughputs or defect levels.
So for now, the initial results for the NXE:3300B remain inconclusive. Still, ASML/Cymer demonstrated 70 Watts of power with the EUV source, which is close to the goal of having an 80-Watt source by year’s end. But the claims were slightly exaggerated. “Under unstated laboratory conditions, 70W was demonstrated for six minutes,” said Chris Mack, gentleman scientist and a lithography expert, in a blog.
All told, there are still more questions than answers about EUV. “The power source is the big issue for EUV today,” Mack said in an interview. “But even if we were to get a viable power source today, that would only allow us to peel the next layer of the onion and see what’s below it. Until we have a high-power source in a tool that processes wafers, we don’t know how bad the mask defectivity problem really is. We don’t know how high-power sources will affect the mask or the optics in operation. And finally, we don’t really know how long it is going to take to solve any of those problems.”
Clearly, the issues and unknowns are contributing to a growing pessimism about EUV. “We think customers have become increasingly frustrated with the slow rate of EUV progress,” said Weston Twigg, an analyst with Pacific Crest Securities. “Chipmakers appear resigned to the fact that EUV is late, and understand that it may not ever be fully ready for mass production. So, there is an intensifying focus on how to extend immersion lithography.”
Why is EUV important?
Indeed, to extend 193nm immersion, the industry is stepping up its efforts to develop new multiple patterning schemes, such as self-aligned double/quadruple patterning and directed self-assembly (DSA).
Still, EUV is critical and for good reason. The ability to print clear features is limited by the wavelength of light. Today’s single-exposure, 193nm lithography reached its physical limit at 40nm half-pitch, but the industry has extended optical by playing tricks with light.
These tricks, called resolution enhancement techniques (RETs), also add cost and complexity to the mix. For example, using 193nm immersion, the shift from single exposure at 28nm to multiple patterning at 20nm is projected to increase lithography costs by up to 56%, according to Barclays Capital.
These costs are expected to soar at 14nm and beyond. So, in theory, EUV is attractive because it keeps the industry on a single-exposure path, thereby keeping costs in check. For cost reasons alone, EUV is critical for next-generation chips, said Lars Liebmann, a distinguished engineer at IBM. “I am rooting for EUV,” he added.
Liebmann noted that his livelihood at IBM revolves around developing multiple patterning solutions, but he is also a big supporter of EUV. If lithographic costs continue to climb, then chipmakers likely will stay at the 28nm node, or other mature technologies, for a longer duration, he said. “That cost is also taking away the motivation (among chipmakers) from moving to the next node,” he said.
This gloomy scenario implies that fewer designs would move into production at each node due to cost factors. Chipmakers, in turn, wouldn’t be able to fill their fabs. And then, Moore’s Law could come to a screeching halt. “If we don’t find a new solution, we could be at the end of the line,” Liebmann said.
Even if EUV is late and inserted at 7nm, the technology still has advantages over 193nm immersion and multiple patterning, said Pawitter Mangat, senior manager and deputy director for EUV lithography at GlobalFoundries. “EUV can still do things that optical can’t,” Mangat said.
Still, EUV would require a multiple pattering scheme at 7nm. EUV with double patterning is 2.5 times the cost per wafer, as compared to 193nm immersion with double patterning, according to Nikon. Meanwhile, in one cost-of-ownership model, Imec compared the processing costs in ideal conditions between single-exposure EUV versus 193nm immersion and multiple patterning at 7nm.
In one application, Imec looked at gate patterning. Surprisingly, an EUV tool with a throughput of 50 wafers per hour (wph) increased gate module processing costs by almost 120%, as compared to 193nm immersion with multiple exposures, according to Imec.
For the same application, EUV at 85 wph reached cost parity with 193nm/multiple-exposure. “If we reached 150 wafers per hour (with EUV), then we can see a 13% benefit,” said Arindam Mallik, a research specialist at IMEC. “From a cost point of view, the FEOL may not be the first place you can go (with EUV).”
EUV also had mixed results for the middle-of-the-line (MOL) of interconnects. Compared to 193nm/multiple-exposure, EUV reached cost parity at 70 wph to 90 wph, Mallik said. At 150 wph, EUV reduces MOL costs by 26%, he said.
In the backend-of-the-line (BEOL), EUV fared much better. EUV at 50 wph reached cost parity with 193nm/multiple-exposure. “If you go to 150 wph, it can reduce the cost by almost 30%,” he said.
Source of the trouble
Clearly, the viability of EUV is dependent on throughput and other factors. “It really comes down to one thing—cost,” said Matt Nowak, senior director of advanced technology at Qualcomm. “But right now, we need EUV to step up and see what it can do.”
As before, the biggest challenge with EUV is the power source, which determines the overall throughput of a system. At one time, ASML/Cymer promised to ship a 100-Watt source by the end of 2012, but the system remains delayed. To date, the source only generates 10-Watts of power, enabling a throughput of less than 10 wph. At that rate, EUV is nearly impractical for mass production.
The production model, the NXE:3300, is in the same boat. “The (NXE:3300) scanner is well on track,” said Mark Phillips, engineering manager for lithography at Intel. “Really, it’s the source, where the availability and power is critical. We need a full 80 Watts with pre-pulse sources in the field for the 3300 scanners. This isn’t enough power for high-volume manufacturing, but it’s enough to start technology development and re-establish confidence in EUV lithography.”
For mass production, the industry requires a throughput of around 126 wph. “The wafers per hour needs to be greater than 100,” said Anthony Yen, director of the Nanopatterning Technology Infrastructure Division at TSMC. “We would first like to get 80 Watts, then 125 Watts and 250 Watts.”
In response, ASML/Cymer has set new goals for the source. By year’s end, it plans to ship an 80-Watt source, enabling an EUV throughput of 58 wph. By 2015, ASML/Cymer hopes to ship a 250-Watt source, which translates to 126 wph.
The EUV source is based on a laser-produced plasma (LPP) technology. In LPP, plasma is generated by a laser pulse hitting a target. The source also makes use of a pre-pulse laser and a master-oscillator power amplifier (MOPA). The lasers are directed at droplets of tin, which fall at a rapid pace from a droplet generator in the system. When hit by the pulsed laser, the tin heats the fuel to create a plasma.
The challenge is to hit the tin droplets in a controlled and precise fashion. “There are disturbances to the droplets that are caused by the flow of hydrogen and by the plasma event itself,” said David Brandt, senior director of EUV marketing at ASML/Cymer.
To help solve the problem, ASML/Cymer is developing what it calls new “control strategies” in an effort to lower the dose margin, which, in simple terms, is the amount of energy that the source consumes. “Typically, we have been operating at 35% margin,” Brandt said. “We work to create energy, but we don’t want to give it away.”
ASML/Cymer has not incorporated the new control systems in the sources yet, but it has demonstrated the ability to lower the dose margin to less than 10%. “A 3.5X reduction in the dose margin enables us to operate at 70 Watts stabilized energy,” he said.
In addition, ASML/Cymer has devised an in-situ cleaning technology for the source. Based on a hydrogen-radical cleaning methodology, the technology removes unwanted tin on the collector in the source. “We can save cost and downtime,” he said. “We can now clean the collector in the vessel without taking it out. You would use this system frequently to remove a nanolayer of tin that isn’t even visible.”
Meanwhile, another EUV source vendor, Gigaphoton, has achieved 43 Watts of output at 100-kHz from its second prototype LPP source for EUV. In addition, Gigaphoton has been developing a new tin droplet system for its EUV source as a means to boost the power within the system.
“We succeeded to realize a 20 micron droplet. The volume is 34 pico-liters. The frequency is 100KHz and spacing is 480 microns,” said Hakaru Mizoguchi, vice president and chief technology officer of the company. Gigaphoton aims to achieve a 150-Watt output on its prototype system by the end of 2014, and 250-Watt output on a high-volume system by 2015.
If ASML/Cymer and Gigaphoton miss their new and respective schedules, then the industry must once again reset its insertion goals with EUV. Then, the uncertainties and doubts will continue to mount for EUV. The industry won’t necessarily give up on EUV, but chipmakers will then face a long, painful and expensive period with multiple patterning.