How packaging houses compare to foundries, and what impact consolidation will have on different IC manufacturing segments.
Semiconductor Engineering sat down to discuss the IC-packaging industry, foundries, China and other topics with Tien Wu, chief operating officer at Taiwan’s Advanced Semiconductor Engineering (ASE), the world’s largest outsourced semiconductor assembly and test (OSAT) vendor. What follows are excerpts of that conversation.
SE: What is your overall outlook for 2016?
Wu: Last year, the semiconductor industry came in at minus 1.9%. This year, Gartner says the industry will grow 1.9%. What that does is move us back to zero. From that particular projection, you already know everybody is very cautious. At this point, there are a lot of economic uncertainties. I can say that the inventory control issues have come to an end. Right now, the industry is seeing an end-demand issue.
SE: Any other problems?
Wu: The industry has not been aggressively investing for the last few years. Look at the front-end investment and backend investment since 2012. For three to four years, the industry has been investing below average. So I do believe when the demand recovers, there will be a shortage of capacity.
SE: Let’s move to the business side. The IC industry is undergoing a wave of consolidation. The EDA, foundry and OSAT industries have seen their share of consolidation as well. What’s driving all this?
Wu: Consolidation is not contained within a particular segment. You are seeing overall consolidation from all corners. With this consolidation, you have to ask yourself what’s the basic driving force? The driving force is that there is more competition in a slower growth environment.
SE: What else is driving the consolidation in the industry?
Wu: So for any company who wants to have longer sustainability, and in lieu of the growth environment and the potential competition, they have to figure out how to differentiate themselves. Differentiation means you have to have better economic scale. You must have better control of your P&L baseline. You must have more R&D dollars to do future investments. You must have a better attraction to the talent pool, which is reducing because of slow growth. So, you have to have better differentiation. In order to have differentiation, people believe that consolidation, at least in a horizontal sense, is one of the best known methods.
SE: The soaring cost of R&D and capital spending is also driving consolidation in the industry. At one time, IC-packaging houses could set up a manufacturing line for several million dollars. What are the capital spending requirements for OSATs at the leading-edge today?
Wu: When a foundry is spending $10 billion to $15 billion to build a new fab, it will cost us $100 million to $200 million to build a packaging line.
SE: Many say there are too many OSATs chasing after a shrinking customer base. Therefore, the OSAT business needs to consolidate. Would you agree?
Wu: First, I want to point this out. How many foundry players are there in the world right now? There are about 10. How many EDA players? You would be challenged to name five. The same is true in EMS. How many OSATs are there? The reality is that there are 100. Of those, you can name 10 players with good revenue. This means revenue of $200 million to $300 million and above. They are not small. So, in any case, the upstream and downstream industries have experienced more consolidation than the OSAT business. Given that the industry customers are consolidating, and the potential differentiation requirements and escalating costs, I believe it is the right thing for the OSATs to have accelerated consolidation.
SE: Some foundries, namely Intel, Samsung and TSMC, are expanding their efforts into packaging, especially at the high-end. These foundries appear to have the R&D dollars and technology to compete with the OSATs. Do these foundries have an advantage over the OSATs?
Wu: You look at the vertical conglomerates. When they do packaging, do they have an intrinsic advantage? In some respects, the answer is yes. They will have a better sense of design for manufacturing from the IC chip design to the foundry process and all the way to packaging. They will have an integrated P&L. That means they understand how to allocate R&D dollars and cost.
SE: What else?
Wu: The foundries also have an intrinsic disadvantage. For example, they are not a dedicated OSAT. They are not a dedicated packaging house. If you go with a company to do the foundry, and maybe the chip design and packaging, customers may lose a portion of their supply chain flexibility. That involves pricing, capacity or the need to have multiple suppliers.
SE: Any thoughts about TSMC’s efforts in fan-out?
Wu: TSMC is doing the industry a service to make fan-out as one of the potential standards for highly-integrated and ultra high-end processor/memory type of packaging. On the other hand, there will be other types of fan-outs that will be developed for different clientele at different price points. They will be targeted for different applications and wafer technologies.
SE: China is making a number of moves to expand into the chip-packaging market. For example, JCET recently bought STATS ChipPAC. In addition, China’s Tsinghua Unigroup has taken separate stakes in two Taiwan OSATs—ChipMOS and Powertech. Any thoughts?
Wu: In general, China’s aspirations in the semiconductor industry are great. Any infusion of new capital into the industry, and to grow the industry to the next stage, in my view, is all good. The only concern is how do we make sure the newly injected capital can have a balanced approached in terms developing IP differentiation and capacity at the same time.
SE: Can you elaborate?
Wu: What happened in LED, solar and display was an example of this aspiration in China. There was a lot of injection of capital and dollars from China into these markets. But the majority of the aspiration and dollars ended up on the capacity side. It collapsed the price without moving the R&D forward.
SE: So what does China to consider as it invests in the IC sector?
Wu: R&D, capacity and pricing need to go hand in hand. If they are taking a balanced approach, then it’s all good.
SE: ASE is in the midst of an unsolicited bid to acquire Taiwan’s Siliconware (SPIL), the world’s third largest OSAT. What’s the latest?
Wu: We already have a 24.99% stake. We have made a second tender offer. If the tender offer is successful, we will have a 49.71% stake in SPIL. Then, we intend to do a 100% acquisition with SPIL. All this is public information. We are following anti-trust regulations on a global basis.
SE: If you succeed in your bid, what does SPIL bring to the party in general?
Wu: That will bring a benefit to customers. If the industry players can consolidate, it will bring more R&D dollars to the high-end, mid-range and also the ultra high-end. In the ultra high-end, we are talking about large investment dollars. We are trying to come up with something close to InFO [Integrated Fan-Out], for example, but cheaper. To do that, you have to have resources and dollars.
SE: What else?
Wu: In the high end, you have copper pillar, panel fan-out, PoP and other advanced wafer-level packaging and flip-chip. The industry is looking for additional R&D dollars to make performance and cost one step higher than the existing state. Even in wirebond, people are looking for what is the next step. Then, it goes to leadframe, QFN, QFP and BGA.
SE: Let’s move to the technology. Moore’s Law has been the guiding principal for leading-edge chip makers. In contrast, chip-packaging doesn’t necessarily follow Moore’s Law in the strict sense of the word. Does Moore’s Law apply to IC-packaging?
Wu: If you look at foundries, they are pushing towards 10nm and potentially 7nm. So as Moore’s Law becomes more expensive, the chips become more expensive. And the packaging needs to be more precise. We need to package more expensive chips in a smaller scale. So, you also need to evolve with Moore’s Law.
SE: Not all chips are leading-edge, right?
Wu: A better question to ask is, ‘Do you think that 7nm and 10nm will take over the whole world? Or do you think 40nm and 28nm will be developed more pervasively by companies? And when that is done, what are the packaging requirements associated with the majority of chips?’ The vector is pointing towards highly heterogeneous and differentiated chip integration.
SE: In general, how do you see the 2.5D stacked die rollout going in the industry in 2016?
Wu: Given the steady volume implementation over the past year, the industry is now coming to the realization that 2.5D is indeed real, and there’s much greater clarity about where the application spaces lie. We will see greater adoption in design and application during 2016, and speed of the adoption will accelerate as the infrastructure, in its entirety, comes into maturity.
SE: How do you see advanced fan-out going in 2016?
Wu: For consumer applications, the market is already driving high-volume production. The implementation of high-density fan-out and for SiP integration applications will take longer.
SE: Besides 2.5D, fan-out and other technologies, ASE is also pushing system in package (SiP). What is that all about?
Wu: SiP has emerged as the best avenue to add value to the product for the whole ecosystem. Essentially, SiP serves to integrate heterogeneous components and functionalities into the most efficient form factor while optimizing cost of ownership.