The List Of Unknowns Grows After Silicon

Third in a series on alternative channel materials for post-silicon devices: InGaAs gate stacks

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As discussed earlier in this series, most proposed alternative channel schemes depend on germanium channels for pMOS transistors, and InGaAs channels for nMOS transistors. Of the two materials, InGaAs poses by far the more difficult integration challenges. Germanium has been present in advanced silicon CMOS fabs for several technology generations, having been introduced used in strained silicon structures since 2006 or so. InGaAs, in contrast, is completely new to the silicon CMOS industry.

It is not a new semiconductor. InGaAs high electron mobility transistors (HEMTs) are used in radar, millimeter wave and microwave communications, and similar high-gain, low-noise applications. However, existing InGaAs process flows are as likely to mislead as to inform potential schemes for integration with silicon CMOS. HEMTs usually use In0.53Ga0.47As, chosen for lattice compatibility with InP. While this composition is well understood, and has been the basis for most studies of potential InGaAs-MOSFET schemes, it is not inherently superior to other choices. Moreover, both InP and In0.53Ga0.47As have an 8% lattice mismatch with silicon. Defects arising from this mismatch are a serious potential problem for silicon integration, but haven’t needed to be addressed in research on InP substrates.

As previously discussed, blanket deposition of InGaAs, followed by a subtractive transistor formation process, is intuitively appealing but may not be desirable. Fabs would prefer to form InGaAs and Ge structures in parallel, rather than having to deposit and remove a thick layer of first one material, then the other. Dry etching InGaAs is difficult, and either a wet or a dry etch step would introduce highly toxic arsenic-based etch byproducts into the fab waste stream. Molecular beam epitaxy, commonly used in compound semiconductor device manufacturing, is a slow, line-of-sight technique, not suitable for filling trenches and other three-dimensional structures. Relatively few studies have considered metalorganic vapor phase epitaxy (MOVPE) as an alternative, but at the 2011 IEEE Electron Device Meeting, researchers from Intel reported that mobility comparable to MBE InGaAs on InP was obtained with MOVPE deposition on silicon.

Finally, it is not clear how to shrink HEMT transistor structures to the 10nm-scale devices likely to be required when alternative channel materials enter CMOS production. HEMT devices typically have thick oxide dielectrics and are not self-aligned. In silicon CMOS, meanwhile, dielectric thickness is dropping below 1 nm (equivalent oxide thickness) and self-aligned transistors are the norm. InGaAs MOS devices will need to follow suit. They will probably also need to be integrated into FinFET and other multiple gate structures: as researchers from Purdue University pointed out at the 2010 IEEE Conference On Indium Phosphide And Related Materials, III-V transistors face the same short channel effects silicon transistors do, made worse by their lower band gap.

As with silicon, as with germanium, surface quality at the InGaAs/gate dielectric interface plays a major role in overall transistor performance. Compared to elemental semiconductors, though, the InGaAs surface is extremely complex. Depending on deposition conditions and surface treatment, the exposed surface can be In-, Ga-, or As-rich, with commensurate variations in the native oxide composition. Both indium and arsenic oxides tend to decompose at relatively low temperatures, producing a surface dominated by the relatively stable gallium oxides. Several groups used stable Ga2O3 native oxide as their starting point, doping with gadolinium to create a Ga2O3(Gd2O3) (GGO) dielectric layer. Surface oxides can contribute to a high density of traps at the InGaAs/dielectric interface; process designers will need to control the chamber environment carefully to obtain the surface composition they want.

When a clean semiconductor surface is required, several studies, reported in an MRS Bulletin review in 2009, have found that the initial trimethyl-aluminum (TMA) pulse in atomic layer deposition of Al2O reduces the native oxides. It appears, in fact, that positive results achieved with Al2O3 dielectrics can be attributed to this surface cleaning, rather than to the inherent superiority of Al2O3 itself. Researchers at UC Santa Barbara and Pennsylvania State University achieved comparable results using nitrogen plasma cleaning, scaling either HfO2 alone or an Al2O3/HfO2 bilayer dielectric down to 0.6 nm EOT with low interface trap densities. So far, however, no consensus dielectric solution has emerged.

Dielectric deposition does not end the evolution of the dielectric/semiconductor interface, either. Nadine Collaert, manager of III-V/Ge R&D at IMEC, observed that indium and arsenic in particular can and do diffuse out of the semiconductor into the dielectric. Oxygen and other post-deposition plasma treatments can play an important role in stabilizing the interface. As Applied Materials front end technologist Atif Noori explained, the gate stack must be viewed as an integrated process:

  • Surface pre-clean
  • Interface passivation and functionalization
  • ALD high-k dielectric layer or layers
  • Post-deposition treatments

No matter how promising an approach to one of these sub-processes may be in isolation, only integration into a full transistor flow can definitively characterize its performance.

The history of silicon CMOS offers a reminder that the best laid plans of process engineers tend to run aground on such realities of process integration. It took the silicon industry decades to scale from micron-sized devices to less than 25 nm. Yet most devices used in InGaAs process studies are still quite large, with gate dimensions exceeding 100 nm. Further scaling is likely to bring additional challenges, and InGaAs proponents will need to meet a very aggressive timeline to find a place on the CMOS roadmap.

Editor’s Note: The research for this series began before the 2013 IEEE Electron Device Meeting had taken place, and as a result has only mentioned recent developments in passing. The next and final installment remedies this omission, fitting developments from IEDM into the larger picture developed so far.