Who is responsible for ensuring a chip is within its power budget and are they being given the tools to do the job?
The debate continues as to whether power has risen to become a primary design consideration, or if it remains secondary to functionality and performance. What is indisputable is the rise in the importance of both power and energy conservation. As technology improves, additional aspects of the design flow are being affected. With that, the focus for power reduction is shifting from the lower implementation levels up the food chain, but not everything is in place to hand off power and responsibility.
One gauge of importance may be the number of chips that fail because of power issues. According to a recent Forbes article, “The drama for Qualcomm began when rumors started circulating that its Snapdragon 810 processor was overheating, and that Samsung was planning on dropping the chip.” This has not been confirmed and others believe this is not the reason for a possible rejection. But it’s a recurring nightmare among chipmakers.
“If a company cannot get a chip designed in because of power they will regret that and wish they had paid more attention to it,” said Jim Kenney, director of marketing within the emulation division of designers. “The RTL designers have the responsibility, but not the ability to make a lot of impact,” says Mark Milligan, vice president of marketing at Calypto. His colleague, Anand Iyer, director of product marketing, adds that “designers have to take responsibility for power. This can be mandated but even then they need to feel empowered to make those decisions.”
What impact can RTL engineers have on total power? Iyer puts some numbers on it. “We see on average that I/O consumes between 5% and 10% of the power budget, analog is between 20% and 30%, and memory is similar at around 20% to 30%. The big reduction opportunities are in the analog part of the design by moving it to digital. Signal processing applications that used to be analog are now converted to digital, processed and then converted back. It may mean some loss of accuracy but overall this is not significant. For memories, people are building additional operational modes for them, such as drowsy modes. The ease with which these capabilities can be integrated into a chip is becoming more important.”
Few of these areas can be impacted by the design team. Some are defined by standards. “Power dissipated in the I/O is a function of its type and the external loading,” says Alan Aronoff, director of strategic business development at Imagination Technologies. “New I/O standards that use lower supply voltages and low voltage swings are designed to minimize the power consumption.”
Aronoff sees the driving factors for minimizing power as the chip architecture, IP architecture and selection, and the selected semiconductor process technology. “Semiconductor technology choices influence the clock speed and ability to deploy voltage scaling. The IP architecture (such as the CPU) will influence the clock speed requirements needed to achieve the targeted level of functional performance. The chip architecture will determine if specific power savings techniques such as dynamic voltage and frequency scaling (DVFS) can be implemented.”
With so much of the power budget tied up in IP and other components, which are out of the RTL engineer’s control, what can be done? “When we were working in the wireless space, we would find that engineers struggled to save the smallest degree of power consumption in the digital baseband, only to find that guys designing the power transistors squandered these savings with a tiny change to their designs,” says David Kelf, vice president of marketing for OneSpin Solutions. “I believe that power is unusual in that, unlike timing across a design, power consumption might be radically different for some components. This can lead to a culture where the most power hungry part of the design sets the bar for power savings elsewhere. Why tweak the datapath only to find that these savings are meaningless in the RF parts of the design?”
We can also question if the RTL engineers have even been given adequate tools to do their job. “If they do not have a solid, accurate RTL estimation tool, then there can be no accurate optimization flow in place, and there can be no effective way to do exploration at RTL, plus they are not power experts to begin with,” says Milligan. “There is a power team that tends to get involved as the design gets more solidified. We give them a full set of tools for timing, we give them a full set of tools for test, but the methodologies for power are still being worked out, and often based on best guesses.”
The bifurcation of power responsibility has now stretched to both extremes of product development. “Currently, platform power management broadly falls under two categories,” says Vinod Viswanath, director of research and development for Real Intent. “At one end are low-power optimizations implemented by hardware designers like transistor/gate/RTL Gate-Level Power Optimizations, RTL Power Optimizations, and optimizations to the processor pipeline. These optimizations are done quite independent of the rest of the platform components, and in most cases, hardware is the best judge of what optimizations to use. On the other end are the limited power management techniques that are available to the operating system and devices to control.”
This possibly calls for power to be centrally managed rather than making each engineer responsible for the individual pieces. “There is a certain amount you can do at the transistor level, a certain at layout, some at the design of the cells, you could use techniques such as synthesis that optimize and do automatic clock gating etc, but 80% of the power savings comes from the architecture,” says Drew Wingard, chief technology officer at Sonics.
This is a common cry within the industry. “Once you have locked the architecture, any changes are incremental in nature,” says Preeti Gupta, director for RTL product management at Ansys. “You can change threshold voltages to save some leakage power or adjust how many power gating switches to use, but you are not deciding how many voltage domains or power domains you need.”
This means that responsibility and ability are not in the same place. “Asking RTL engineers to solve the problem is the wrong model,” says Wingard. “It is the architect’s job and that is where the lack of good models is a big barrier.”
“RTL designers have been concerning themselves with power for a while, but it hasn’t really shown up on the radar of many system architects,” says Bill Neifert, chief technology officer at Carbon Design Systems. “It’s not being positioned as their problem, so in all but a few cases, they’re not making an effort to tackle it.”
Are the architects better equipped to make these choices? “What is happening at the system level was traditionally a very abstract view of the world that has been devoid of the physics underneath,” explains Alan Gibbons, power architect within Synopsys. “We have now pulled real world physics into the system-level design arena. This requires software developers and architects to look at some of the physical implementation issues and those are skill sets they need to acquire.”
This is a big change. “If we look at how the architects dealt with these issues in the past, it was really spreadsheet analysis in a static manner, and what they are finding is that the relationship between power management and performance becomes more critical and they can no longer rely on static calculations,” says Pat Sheridan, product marketing for virtual prototyping at Synopsys. “They are shifting to use more dynamic simulation so the architectural version of the virtual prototype can realistically reproduce the application workload and show the dynamic effects on different parts of the system in terms of performance and power.”
Norman Cheng, vice president and senior product strategist at Ansys, describes the ways things have been done in the past. “At the architectural level the total power for a smartphone may be defined as 10 watts. That trickles down to the individual components where the CPU cannot be more than 3 watts, and everyone has a budget. The final goal is for the system architect to determine if power shuffling enables the end goal to be met.”
But this is where the next level of problem starts both for the RTL developer and the IP provider. “They often don’t know how the chip will be used from an application perspective, so predicting power numbers is very difficult,” points out Jean-Marie Brunet, director of marketing within the Emulation Division of Mentor Graphics. “This requires knowing what the activity will look like.”
Viswanath adds that “optimizations are done in isolation without utilizing the knowledge of the workloads. Due to a lack of hardware/software cooperation in power management, the platform as a whole cannot anticipate power requirements of the application ahead of time and instead, has to perform power management reactively.”
Aronoff agrees: “The use cases define the active paths, clock frequency and other parameters needed to estimate power in the device.”
Power management extends to many aspects of chip design. “In most IC design houses, methodology experts come up with a global pessimistic power grid spec to meet worst case power and EM/IR requirements. These are replicated by chip designers in their physical design flow,” says Nayan Chandak, senior area technical manager for Ansys. “However, this overdesigned grid is leading to serious routing congestion and timing closure challenges for finFET based designs.”
Chandak lists a number of problems that can be created by bad high-level decisions. “The presence of multiple power domains introduces additional challenges like ensuring adequate ESD protection circuitry between all possible domain pairs. Similarly, introduction of power gating greatly reduces the off-state leakage, but introduces additional risk associated with high rush current and noise coupling during wake-up operation. The move to finFETs brings lower leakage and faster performance, but also much lower noise margins (higher switching current density coupled with lower operating voltages), and hence serious power integrity and reliability (EM/ESD) challenges. The system architect has to put together the scenario and then, for each component of the chip, to define the peak duration power for that scenario and the most plausible combination of the scenario. This has to be determined in advance so that you don’t miss important corner cases.”
Once the architects have discovered the right scenarios and have more information about power budgets, this information has to be passed down the chain. “RTL designers are given a functional specification, and if you get this done in this number of cycles then my architecture is okay,” says Wingard. “They are not given enough contextual information to know how much power they can use for different things. The power spec they are given is inadequate. It is not a single number. These blocks are used in so many ways, with different data rates and different data sets and these all affect power.”
Steve Carlson, vice president of marketing for low power and mixed-signal solutions at Cadence, agrees. “The guys doing the implementation just get a file from someone for their switching activity. They don’t know what it does. There is a disconnect between the ones deciding on the stimulus sets and those using the information.”
Viswanath lays out the challenge facing the industry. “It is imperative that a holistic platform-level dynamic power management system be aware of: (a) different power states supported by different components, both at the architectural and micro-architectural level; (b) power consumption for the platform as a whole, and at the individual component level; (c) power requirements of applications and workloads, and, (d) continuous feedback from the platform on performance with respect to overall power constraints. We need all levels of abstraction of the design to be able to communicate their power intent.”
Just in case you are thinking that power problems only affect a small part of the industry, Nachiket Kapre, chief technology officer at Plunify tells us what it is like for FPGA developers. “To make good use of High Level Synthesis (HLS) in an FPGA flow is to generate different HLS candidate solutions in a controlled fashion, implementing them via the Place and Route (P&R) tools and using the results to drive convergence. This feedback helps build a more accurate model that can fully account for the noise inherent in the FPGA P&R heuristics and the interaction between the input problem, the HLS and the P&R algorithms.”
Mentor’s Kenney takes it up another level when talking about power constraints designing server racks in a data center. “Power consumption implies cooling and refrigeration is expensive. Power density is important in a data center. If you have a rack that’s six feet tall and the data center is designed for 10 kilowatts, then if you exceed that density you have to leave more space around the system because you can’t power it or cool it. If you fit within the power density, then you can pack the machines closer together.”
Several IEEE standards groups are attempting to define many of the missing technology pieces, including IEEE 1801, IEEE P2415, IEEE P2416. “Participation in the UPF group is impressive,” says Gibbons. “System architects and power architects from all of the major mobile platform providers, a lot of activity from IP companies, graphics houses. They are very keen to see interoperability between system-level power models.”
Accellera officially formed a new working group, the Portable Stimulus Working Group , on Feb. 11, to tackle the problem of creating use-case scenarios that can be used for power analysis. Portable stimulus should provide a standardized way of capturing these scenarios and the same tests should become portable throughout the design flow, meaning that the RTL engineers should be able to run the same scenarios.
Things are changing. “We are starting to see organizational and management changes related to who has the responsibility for power and how we enable them to take that responsibility,” says Milligan. “Design for test was similar in that it was thrown over the wall to some experts and over time we were able to move it up.”