Achieving Reliable 2m+ DAC Connectivity For AI Scale Networks With 224G PHY IP

As artificial intelligence workloads and hyperscale data centers continue to evolve, the requirements for networking infrastructure are becoming increasingly stringent. High-speed, reliable connectivity is essential to support the massive data flow and low-latency demands of AI-scale environments. Passive direct attach copper (DACs) remains an attractive choice for hyperscalers and system vendors in this context due to their low cost, minimal latency, and substantially lower power consumption than optical or active copper interconnects. However, achieving robust performance over long DAC cables is extremely challenging—they are considered one of the most difficult channel types for high-speed SerDes links. Recent silicon validation results for Synopsys 224G PHY IP demonstrate a significant step forward in addressing these challenges and enabling reliable 2m+ DAC connectivity for AI-scale networks.

Context: Silicon validation and interoperability

Fig. 1: 224G PHY IP silicon validation and InterOp journey.

The validation journey began with the introduction of a 224G PHY IP test chip, fabricated on a 3nm node in July 2024. Initial efforts focused on electrical characterization at static voltage and temperature, using channels with losses from 10 to 45 dB and applying external crosstalk to simulate real-world noise conditions. These tests help ensure the PHY can handle the densely packed, interference-prone environments typical in modern data centers.

Next came formal characterization across process, voltage, and temperature (PVT), following the IEEE 802.3dj standard. The primary goal was to achieve zero post-FEC (Forward Error Correction) symbol errors and to validate interoperability with a variety of ecosystem partners. These included cabled backplanes, midplane connector boards, and early direct attach copper cables. This comprehensive testing is critical to ensure consistent, error-free performance across a wide array of configurations.

From June 2025, the scope of testing expanded to include the latest generation of DAC cables using a new system validation board equipped with OSFP connectors. This setup allowed for extended reach testing, simulating practical deployment scenarios in AI-scale data centers.

Validation board and results

A central part of these results comes from system-level testing on a validation board with OSFP connectors. This board enabled testing of the 224G PHY IP with new-generation DAC cables from multiple vendors, at lengths of 1m, 1.5m, and 2m. The challenge with DAC cables, especially at longer reaches, is maintaining signal integrity and minimizing bit error rates (BER) under high-speed conditions.

The data shows that the 224G PHY IP consistently achieves ultra-low BER—between 2E-9 and 5E-10—even at 2 meters, which is double the reach specified by current industry standards. This performance was observed across multiple cable vendors, highlighting the robustness of the PHY’s architecture and its ability to handle demanding channel conditions.

Fig. 2: 224G PHY IP in 3nm: BER performance vs DAC length.

Fig. 3: BER performance surpasses spec by 100,000x enabling maximum link reliability.

Key benefits for data center deployments

These validation results offer several practical benefits for data center architects and operators:

• Significant BER Margin: The pre-FEC BER achieved with new DACs is 100,000 times better than the 224G-LR specification. This provides a wide safety margin for link robustness after FEC, helping maximize system reliability and uptime.
• Extended Reach: Achieving stable performance at 2m (and beyond!) with DACs enables more flexible and cost-effective data center topologies. Operators can reduce reliance on retimers, active copper cables and optics, simplifying infrastructure, reducing power consumption, and lowering costs.
• High Reliability Over Time: Long-duration tests showed zero post-FEC errors, with the worst case being a single 5-symbol error event. This demonstrates a substantial post-FEC margin, supporting error-free operation even as environmental conditions change.

Architectural highlights enabling reliable connectivity

The ability of the 224G PHY IP to deliver robust performance over challenging channels is rooted in its architectural innovations:

Fig. 4: Newly designed, high-precision architectural components enable 224G per-lane speeds.

• Analog Front End: The receiver architecture features a redesigned analog front end with enhanced bandwidth and signal integrity compared to previous generation 112G PHYs. Components like continuous time linear equalizers (CTLE) and variable gain amplifiers (VGA) boost and optimize signals to reduce the burden on digital processing.
• Advanced Digital Equalization: The RX DSP employs multiple equalization techniques that work in conjunction—feed-forward equalization (FFE), decision feedback equalization (DFE), floating tap equalization, and maximum likelihood sequence detection (MLSD)—to mitigate inter-symbol interference and reflections.
• Adaptive Calibration: The PHY continuously adapts both analog and digital parameters to maintain optimal performance as channel conditions evolve. For protocols supporting link training, it can recommend remote transmitter equalization adjustments to further improve reliability.  During mission mode, the PHY can dynamically adjust equalization coefficients and calibration values, responding to changing environmental conditions without resetting the link. This adaptability is crucial for maintaining up time in dynamic data center environments.

Implications for AI-scale networking

These silicon validation results show that reliable 2m+ DAC connectivity is achievable for AI-scale networks, addressing a key challenge in high-speed data center design. Synopsys 224G PHY IP is already being integrated into customers’ network interface cards, data processing units, retimers, and optical modules supporting next-generation AI and high-performance computing systems.

With proven reliability and extended DAC reach, this technology enables operators to confidently scale their infrastructure to meet the growing demands of AI workloads and hyperscale deployments, ensuring both bandwidth and signal integrity.

See the results in action

For a closer look at the validation process and real-world demonstrations—including the system validation board and performance charts—watch our video. The session provides insights into the architectural advances driving reliable, extended reach over DAC cables.