Advanced Packaging Driving New Collaboration Across Supply Chain

The semiconductor industry is undergoing a profound shift in packaging technologies to ones that rely on close collaboration among multiple stakeholders to solve intricate, multi-faceted, and extraordinarily complex problems.

At the heart of this change is the convergence of heterogeneous integration, chiplets, and 3D stacking. Heterogeneous approaches allow companies to combine different technologies — such as logic, memory, analog, and RF — into one package, improving both performance and cost efficiency. It also allows them to target specific domains or workloads, leveraging chiplets and pre-integrated modules that can be assembled into a unified system.

Chiplets enable companies to mix and match different silicon processes on separate dies. But achieving this modularity requires tight coordination across the ecosystem — from substrate design and interposer development to assembly and testing. Put simply, no single company can manage every aspect of the development cycle, no matter how large or advanced they are.

“There’s an enormous amount of variation in advanced packaging,” says Dick Otte, CEO of Promex. “We have a wide range of substrate technologies available, and they’re evolving rapidly. Similarly, there are many different ways that dies are made, and the assembly processes themselves are becoming more diversified. All of these variations add to the complexity of advanced packaging, and it’s clear that no one-size-fits-all solution will work. The challenge for the industry is figuring out how to align these various technologies into a cohesive process that drives innovation forward.”

The need for a collaborative ecosystem among companies was a major topic at the NIST Advanced Packaging Summit this year. The summit highlighted how the growing complexity of semiconductor packaging, especially in chiplets and heterogeneous integration, is creating challenges that no single entity can tackle independently.

“None of us is going to do this alone,” said Erik Hadland, director of technology policy at the Semiconductor Industry Association (SIA). “This is a diverse and complex industry, and we need everyone to broaden their thinking about how we might do this better, smarter, and faster.”

Industry leaders, government representatives, and academic experts all agreed that advancing packaging technologies will require deeper cooperation between foundries, integrated device manufacturers (IDMs), outsourced semiconductor assembly and test providers (OSATs), equipment vendors, and materials suppliers. A lack of collaboration not only slows down the development cycle but also threatens to stifle innovation, particularly in areas such as AI hardware, 5G/6G, and automotive systems, which depend on high-performance packaging solutions.

“The opportunity for advanced packaging has never been greater, but it also comes with significant challenges,” said Audrey Charles, senior vice president of corporate strategy at Lam Research, and president of Lam Capital. “What’s become clear is that working together is essential to overcoming these hurdles.”

Complexity is driving collaboration
The advanced packaging landscape today is characterized by a wide variety of materials, interconnect methods, and design choices, each of which introduces unique challenges. The industry is moving beyond traditional organic substrates, such as FR4, to silicon-based interposers that allow for higher densities and more complex routing schemes. In particular, the shifts toward silicon interposers and glass substrates are creating opportunities for more compact designs, but they also introduce new challenges related to thermal management, warpage control, and planarity.

“The packaging landscape is incredibly complex, and today, it’s all about managing a multitude of variables,” says Otte. “A critical piece of this puzzle is substrate dimensions, which form the foundation for innovation in advanced packaging. Traditionally, we’ve worked with 75mm lines and spaces on circuit boards, but we are now pushing those limits significantly. In organic substrates we’ve moved into the 25mm regime, and for silicon-based interposers we’re seeing dimensions as small as 5 to 7mm. This shift into chiplet interposer territory — what I consider the true frontier of advanced packaging — demands a complete rethinking of processes and capabilities.”

Chiplets promise flexibility by allowing companies to combine in the same package high-performance logic dies developed at the most advanced process nodes with memory, RF, and power management units developed at mature nodes. This is particularly important in applications like AI, 5G, and data centers, where the performance requirements are continually increasing, but traditional monolithic SoCs are becoming too expensive to manufacture.

“The chiplet ecosystem is crucial for any implementation of advanced packaging,” said Bapiraju Vinnakota, program manager for the National Advanced Packaging Manufacturing Program (NAPMP). “By leveraging chiplets, companies can reduce costs, improve performance, and accelerate time-to-market, but only if there’s a strong collaborative ecosystem in place to support the technology.”

The sheer diversity of substrate materials, interconnect technologies, and packaging architectures makes collaboration essential. Each stakeholder, whether it’s a substrate manufacturer, foundry, assembly house, or equipment vendor, brings a unique set of skills and knowledge to the table. A lack of alignment between these entities can lead to bottlenecks, delays, and ultimately product failures.

“Collaboration among chip designers, manufacturers, and system integrators is essential for building a successful design ecosystem,” said Lihong Cao, senior director at ASE Group, in a recent presentation. “Advanced packaging offers solutions for chiplets and heterogeneous integration, but there is a need to build up the ecosystem.”

In high-performance applications, such as those found in data centers, the demands on power delivery, signal integrity, and thermal management are exceptionally high. For example, a typical AI chip in a data center might have thousands of input/output (I/O) connections, each requiring precise alignment and thermal control. Failure to provide adequate thermal dissipation can lead to overheating, which degrades performance or causes permanent damage to the device.

“Typically, chips at advanced nodes are much more fragile, and the interface requirements are different from older nodes,” says Calvin Cheung, vice president of engineering at ASE Group. “You need to balance the stress between different technologies in the same package, and that requires close collaboration between the design and packaging teams.”

This is particularly true for thermal issues in high-performance, multi-chiplet packages. “AI chips, in particular, dissipate a lot of heat, and with large modules, managing that heat distribution and controlling warpage are critical challenges,” said Vik Chaudhry, senior director of product marketing and business development at Amkor. “We are defining best practices to help the industry address these challenges, but there’s no one-size-fits-all solution.”

Collaboration barriers
One of the most significant barriers to collaboration is effective communication between organizations. With design and manufacturing processes increasingly spread across different regions, time zones, and languages, just ensuring that all stakeholders are aligned is extremely difficult. This problem is compounded by the complexity of the technologies involved, which often require highly specialized knowledge.

Cross-border communication barriers, whether linguistic or cultural, can lead to misunderstandings that slow down development cycles and increase costs.

“Each of us knows our area of expertise in great depth, but the real challenge comes when you try to bridge communication barriers between teams,” says Promex’s Otte. “When you can get a team together that understands each other, it’s most effective to use graphical representations rather than words, especially when working internationally. Many people are speaking English as a second language, which complicates things. Clear communication through images and numbers helps cut through a lot of the confusion.”

Another significant barrier to scaling advanced packaging is the issue of vertical integration among leading technology companies. Major players, such as Intel, TSMC, and Samsung, have developed vertically integrated models where they control every stage of production, from chip design and manufacturing to assembly and final test. This control gives these companies an edge in terms of optimizing processes, as well as defining sockets for third-party chiplets, but it’s not the most cost-effective approach in the long term. Large companies can tightly control the interconnects, thermal management, and substrate designs between their chips, but using well-characterized, and increasingly standardized off-the-shelf chiplets can significantly reduce costs, just as it has for standardized IP.

Smaller companies, meanwhile, have limited access today to a compatible ecosystem of technologies necessary for chiplets to function. Consortiums are experimenting with ways to minimize that handicap for specific applications, enabled by standards such as UCIe, but it will take time before all the pieces — such as standards for interposers and substrates — are in place for broad markets.

“What UCIe is trying to do is standardize that interconnect between vendor A, vendor B, and vendor C,” said Amkor’s Chaudhry. “It allows multiple chiplets to connect and talk to each other, even when they are from different sources, which is critical as we move from 2-die systems to multi-die systems with up to 12 dies in a package. The challenge is significant, and only a few companies globally have the resources and capabilities to handle it. Amkor, TSMC, Intel, and ASE are among the few that can commit the necessary resources and expenses to put these lines together.”

Standardization would help reduce costs and increase efficiency, while playing a critical role in fostering collaboration across borders. The adoption of common standards would make it easier for companies in different parts of the world to work together on advanced packaging solutions, creating a more open ecosystem This is particularly important as heterogeneous integration becomes the dominant paradigm for packaging, where components from multiple vendors need to fit together seamlessly.

“The entire semiconductor industry would be so much stronger if everybody would just trust each other a little bit,” said Mike Mathews, executive director of manufacturing and logistics at Brewer Science. “When I discuss that with senior leadership at industry leading companies they always agree, but that’s about as far as it goes. That’s just the nature of the beast.”

Pilot lines
One potential solution to the barriers created by vertical integration is the establishment of pilot line facilities, which allow smaller companies and startups to access advanced packaging technologies, but without requiring them to invest heavily in their own equipment. These facilities allow companies to test new designs and processes in a controlled environment before committing to full-scale production. The ability to test new ideas in such facilities could help democratize access to advanced packaging technologies, enabling smaller firms to compete with larger, vertically integrated corporations.

“The idea is to have a stable process where new ideas can be tested, and the handoff to higher-volume production is made smoother,” said Carl McCants, special advisor to the director of DARPA. “By providing a space for experimentation and refinement, pilot lines offer a middle ground between pure R&D and commercial-scale production. This not only lowers the financial risk associated with developing new technologies, but also speeds up the time-to-market for new solutions, making it easier for smaller companies to participate in the advanced packaging ecosystem.”

Pilot line facilities are also emerging as a key resource for developing next-generation interposer designs, 3D stacking techniques, and hybrid bonding processes. These technologies are essential for scaling chiplet-based architectures and achieving the performance improvements demanded by high-performance computing, AI, and data center applications.

However, pilot lines are not a complete solution to the challenges facing the industry. While they help alleviate some of the financial burdens for smaller firms, the broader issues of standardization and ecosystem alignment remain. For these facilities to truly unlock the potential of advanced packaging, they need to operate within a framework of industry-wide standards, ensuring that the technologies developed in pilot lines can be seamlessly integrated into larger production ecosystems.

“Advanced packaging is driving scaling across all device segments — not just high-performance compute and logic, but also DRAM and HBM,” said Lam’s Charles. “The key to rising to this challenge is collaboration — working faster and more efficiently together.”

Collaborations beyond technology
In addition to the technical challenges, the semiconductor industry is grappling with a growing skills gap as packaging technologies evolve. The convergence of different domains — electrical, thermal, mechanical, and optical — within a single package requires engineers who possess a broader and more nuanced skill set than ever before. This is a significant challenge for companies, as many engineers are highly specialized in one area, but often lack expertise in other critical aspects of advanced packaging.

To address this growing need, companies increasingly are turning to universities and academic collaborations to train the next generation of engineers. By creating specialized curricula that focus on the unique challenges of advanced packaging, these partnerships aim to equip students with the skills they need to succeed in the industry. Courses that cover topics like chiplet integration, heterogeneous packaging, thermal management, and signal integrity are now essential components of engineering education.

“We need to focus more on building out capabilities to address the growing skills gap in advanced packaging, said Deirdre Hanford, CEO of Natcast, which operates the National Semiconductor Technology Center. “As new fabs are established across the country, we need to develop not just engineers, but also technicians who can support these new technologies,” she said. “There’s a pressing need for specialized curricula that can train the next generation of engineers in areas like thermal management, signal integrity, and interposer design. We’re already seeing interest from universities, but we need to scale these efforts quickly.”

In addition to formal education programs, on-the-job training and apprenticeships also are becoming increasingly important. As packaging technologies become more complex, engineers need hands-on experience with the tools and techniques required to implement these solutions effectively.

Conclusion
Looking ahead, the future of advanced packaging will be defined by how well companies collaborate across disciplines, share knowledge, and align around common standards. Without a unified approach, the industry risks becoming fragmented, with different companies pursuing divergent solutions that are incompatible with one another. This increases costs and slows down the overall pace of innovation.

One of the most pressing needs in advanced packaging is the development of industry-wide standards that ensure interoperability between different vendors and systems. While initiatives like UCIe have made significant strides in establishing a common framework for chiplet interconnects, there is still a long way to go in creating universal standards for substrates, die-to-die communication, and thermal management.

Collaborative ecosystems are not just a strategy for the future. They are an essential factor for the continued growth and success of advanced packaging. By fostering communication, investing in workforce development, and embracing industry-wide standards, the semiconductor ecosystem can unlock the full potential of advanced packaging technologies. No single company can manage these complexities in isolation, which is why collaboration across the supply chain is now more critical than ever.

Related Reading
3.5D: The Great Compromise
Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.
Why Small Fab And Assembly Houses Are Thriving
Megafabs churning out the most advanced processors are not the only game in town.
Precision Patterning Options Emerge For Advanced Packaging
Photolithography is still mainstream, but innovative new solutions are coming.
Controlling Warpage In Advanced Packages
Mechanical stresses increase with larger sizes and heterogeneous materials.
Electromigration Concerns Grow In Advanced Packages
Higher density, heat, and more materials make it harder to ensure reliability.