Analog Planar Memristor Device: Developing, Designing, and Manufacturing
By Technical Paper Link - 20 Dec, 2023 - Comments: 0

A new technical paper titled "Analog monolayer SWCNTs-based memristive 2D structure for energy-efficient deep learning in spiking neural networks" was published by researchers at Delft University of Technology and Khalifa University. Abstract: "Advances in materials science and memory devices work in tandem for the evolution of Artificial Intelligence systems. Energy-efficient computation... » read more

Nanoscale Reconfigurable Si Transistors (TU Wien, CNRS, UNC)
By Technical Paper Link - 20 Dec, 2023 - Comments: 0

A new technical paper titled "Nanoscale Reconfigurable Si Transistors: From Wires to Sheets and Unto Multi-Wire Channels" was published by researchers at TU Wien, CNRS, and University of North Carolina at Chapel Hill. Abstract: "In this work, bottom-up Al–Si–Al nanowire (NW) heterostructures are presented, which act as a prototype vehicle toward top-down fabricated nanosheet (NS) and ... » read more

Memory Devices-Based Bayesian Neural Networks For Edge AI
By Technical Paper Link - 20 Dec, 2023 - Comments: 0

A new technical paper titled "Bringing uncertainty quantification to the extreme-edge with memristor-based Bayesian neural networks" was published by researchers at Université Grenoble Alpes, CEA, LETI, and CNRS. Abstract: "Safety-critical sensory applications, like medical diagnosis, demand accurate decisions from limited, noisy data. Bayesian neural networks excel at such tasks, offering... » read more

FeFET Memory Encrypted Inside The Storage Array
By Technical Paper Link - 20 Dec, 2023 - Comments: 0

A new technical paper titled "Embedding security into ferroelectric FET array via in situ memory operation" was published by researchers at Pennsylvania State University, University of Notre Dame, Fraunhofer IPMS, National University of Singapore, and North Dakota State University. Abstract "Non-volatile memories (NVMs) have the potential to reshape next-generation memory systems because of... » read more

Forward Body Biasing in Bulk Cryo-CMOS With Negligible Leakage (TU Delft)
By Technical Paper Link - 20 Dec, 2023 - Comments: 0

A new technical paper titled "Cryogenic-Aware Forward Body Biasing in Bulk CMOS" was published by researchers at QuTech, Tu Delft. Abstract "Cryogenic CMOS (cryo-CMOS) circuits are often hindered by the cryogenic threshold-voltage increase. To mitigate such an increase, a forward body biasing (FBB) technique in bulk CMOS is proposed, which can operate up to the nominal supply without prob... » read more

Densification Of RF Designs
By Ann Mutschler - 20 Dec, 2023 - Comments: 0

It’s challenging enough to deal with wireless signals at the 5G and 6G frequencies. But with increased density in chips crammed into smaller packages, higher power, beam forming, and MIMO, design requirements are very different than in the past. Simple parasitic extraction no longer is sufficient. Daren McClearnon, product manager for RF and microwave simulation at Keysight, talks about the n... » read more

System-Driven PPA For Multi-Chiplet Designs
By Cadence - 20 Dec, 2023 - Comments: 0

As we approach the device scaling limitations at advanced nodes, the demand on compute performance and data transfer for hyperscale data center and AI designs is at an all-time high. Advanced systems-on-chip (SoCs) are reaching reticle size limits, and there has been a need to find innovative solutions to continue Moore’s law scaling and achieve performance improvements with reduced power. St... » read more

Accelerated Optimization With IC Compiler II
By Synopsys - 20 Dec, 2023 - Comments: 0

Efficient optimization is a necessary, yet challenging aspect of the physical implementation flow. IC Compiler II and the underlying physical optimization engines have been re-thought and re-architected to address these growing challenges. Click here to read more. » read more

A Configurable Test Infrastructure Using A Mixed-Language And Mixed-Level IP Integration IP-XACT Flow
By Arteris - 20 Dec, 2023 - Comments: 0

This paper written with NXP describes an efficient integration flow for mixed-language and mixed-abstraction level IPs through IP-XACT flow automation. Authors Erwin de Kock (NXP), Jos Verhaegh (NXP) and Serge Amougou (Arteris) describe: A configurable and reusable test infrastructure for RTL designs as an application of mixed-level and mixed-language integration using the IP-XACT stand... » read more

Blog Review: Dec. 20
By Jesse Allen - 20 Dec, 2023 - Comments: 0

Siemens' Huw Geddes finds that the flexibility offered by the RISC-V ISA can introduce further verification and validation requirements to ensure that the combination of extensions and customization not just works but does not break anything else while delivering expected performance, plus looks at how processor trace can help. Cadence's Gustavo Araujo explains the various optimizations in t... » read more

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