Bulk CMOS Vs. FD-SOI

The leading edge of the chip market increasingly is divided over whether to move to finFETs or whether to stay at 28nm using different materials and potentially even advanced packaging.

Decisions about which approach to take frequently boil down to performance, power, form factor, cost, and the maturity of the individual technologies. All of those can vary by market, by vendor and by process node. But those decisions also can change quickly because all of these technologies and methodologies are subject to perpetual change and modification.

At a recent event, Thinh Tran, chief executive of Sigma Designs, described the process technology challenges for the Fremont, Calif.-based fabless IC design house. Today, Sigma Designs’ consumer-oriented chips are based on various planar processes at 28nm and above. The company ultimately wants to move its chips to a single process that delivers good performance and low power.

“We need something affordable, because the market we are in is very competitive,” Tran said. “We also need to get to the next node to get the cost down.”

The problem is that no one process fits all applications, and Sigma Designs doesn’t have the resources to develop chips based on finFETs at 16nm/14nm and beyond. “We can’t afford finFETs,” he said. “Our product cycles are so short. And with volumes that are not that big as compared to all of the larger guys, it doesn’t make sense to invest that kind of money. You are never going to get your investment back.”

Other small- to midsize chip companies are facing similar challenges. It’s too expensive to migrate to finFETs, and analog and mixed-signal designs don’t require them. Indeed, the economics are problematic beyond 28nm. In total, the average IC design cost for a 16nm/14nm chip is about $80 million, compared to $30 million for a 28nm planar device, according to Gartner. For that reason and others, many foundry customers will elect to stay at 28nm and above. The 28nm node, particular, is expected to remain a popular for the foreseeable future.

Meanwhile, to keep these leading-edge planar processes competitive over the long haul, foundry vendors are beefing up their offerings. For example, TSMC and others continue to evolve their 28nm bulk CMOS processes. Generally, bulk CMOS refers to a chip built on a standard silicon wafer.

On another front, Samsung is stepping up its foundry activities with 28nm fully depleted silicon-on-insulator (FD-SOI) technology. GlobalFoundries, meanwhile, is readying a 22nm version of planar FD-SOI technology. Both foundries also are expanding their respective third-party EDA and IP portfolios for FD-SOI.

In contrast to bulk CMOS, FD-SOI makes use of SOI wafers, which incorporate a thin insulating layer within the substrate to suppress leakage.

So which path should a foundry customer follow in this confusing landscape? It depends on a multitude of factors. “I wouldn’t say it’s one technology or another,” said Kelvin Low, senior director of foundry marketing at Samsung Semiconductor. “There are many choices available. This is where it’s important for the foundry to sit down with designers and customers to understand the final product-level objectives.”

The challenges
Foundry vendors are expanding their efforts at the planar nodes, and for good reason—the IC industry is changing amid a slowdown in and a rapid increase in R&D costs in the arena. Not long ago, there were a sizable number of foundry customers who followed Moore’s Law and could move to each leading-edge process node. But today, there are fewer customers who can afford to migrate to each node, especially at 16nm/14nm and beyond. This helps explain why the foundry customer base continues to shrink at the cutting edge.

For some time, foundry vendors have been looking for new business opportunities beyond the leading edge. This involves customers who are developing chips that don’t necessarily scale according to Moore’s Law, notably for analog, mixed-signal and RF.

For these devices, the market remains steady. “We’re seeing increased demand for testing RFICs, automotive analog, and various parts of the IoT device supply chain,” said Luke Schreier, director of product management and marketing at National Instruments (NI). “There’s also the explosion of sensor technology. From our perspective, these are really exciting markets as they offer both cutting-edge technical requirements for analog/RF measurements and difficult business challenges for the total cost of test.”

Within this segment, several new and sizeable businesses are emerging. One of those is the (IoT), which is projected to be a $50 billion to $75 billion semiconductor market by 2019 to 2020, according to GlobalFoundries. The IoT chip business involves several applications, such as consumer, industrial automation, medical, smart homes/buildings and wearables, the company said.

Foundry customers, meanwhile, face a different set of challenges. For years, customers could migrate from one planar node to the next with relative ease. Planar technology is well understood and relatively inexpensive.

One planar technology, 28nm, is especially popular. “28nm will be a sweet spot for a long time, especially for cost and the ability to have the right power performance,” Samsung’s Low said. In addition, 28nm technology is relatively inexpensive to manufacture because it can leverage mature and cost-effective single-patterning lithographic techniques.

Many foundry customers would like to scale below 28nm, but it’s more difficult and more expensive. At 20nm, 193nm wavelength lithography reached its physical limit. The path forward requires double patterning, which provides a 30% reduction in pitch and requires two separate lithography and etch steps to define a single layer.

“(Double patterning) is necessary to continue scaling,” said Subramani Kengeri, vice president of the CMOS Platforms Business Unit at GlobalFoundries. “It did not come free. Wafer costs started going up.”

This, in turn, impacts overall chip costs. “Historically, our customers have been used to getting about a 30% die cost improvement from node to node,” Kengeri said. “But that started slowing down beyond 28nm, because the die shrink advantage was offset by rising costs.”

Some foundry customers who can afford those costs are moving to 16nm/14nm. These customers require finFET transistors for high-end applications, such as FPGAs, graphics chips and processors. But a large percentage of foundry customers will never move to 16nm/14nm and beyond.

“One major reason is the economics of moving to 16nm is too costly,” said Yawlin Hwang, vice president of worldwide sales and marketing at Global Unichip, a fabless ASIC design house.

It’s not hopeless for foundry customers, though. Customers have several options and could move down the following paths:

• Stay at 28nm bulk CMOS;
• Move to a new 28nm bulk CMOS variant, or
• Migrate to FD-SOI at 28nm and/or 22nm.

Each foundry customer has a different set of requirements. For example, Sigma Designs bases its process technology decisions on several factors—mask costs, time-to-market, performance, power, and nonvolatile memory and RF IP support. “NRE costs become a very big factor when we consider what technology node to use,” Tran said.

Based on cost alone, Sigma Designs has ruled out finFETs. Now it is looking at several options, including 22nm FD-SOI.

FD-SOI vs finFETs?
And this is where the confusion begins. For example, some industry experts position finFETs and FD-SOI as direct competitors. Still others place finFETs at the high-end of the transistor spectrum, while 28nm and 22nm FD-SOI are seen as a low-power alternative to 28nm bulk CMOS.

Both positions have some merit, but the current thinking leans toward the latter over the former. “Both (finFETs and FD-SOI) have different cost points,” Samsung’s Low said. “14nm finFETs were created for more performance, lower power and more scaling. FD-SOI consists of planar transistors that have very low-power attributes for Internet of Things-type applications.”

FinFETs and FD-SOI have some major differences. For one thing, finFETs are 3D-like structures. In finFETs, the control of the current is accomplished by implementing a gate on each of the three sides of a fin.

Today, GlobalFoundries, Intel, Samsung and TSMC are ramping up finFET processes. And there is a roadmap to scale the finFET from 16nm/14nm to 7nm and perhaps beyond.

In comparison, FD-SOI is a planar technology that requires specialized SOI substrates. Within the substrate, there is an ultra-thin layer of silicon that sits on top of a buried oxide. FD-SOI supposedly provides several advantages over bulk CMOS. In a basic bulk CMOS transistor, there is a source and a drain. Current flows from the source to the drain through a channel.

As chipmakers scale transistors at each node, the channel length becomes shorter. As a result, the channel may suffer from so-called short-channel effects. This, in turn, degrades the sub-threshold slope, or turn-off characteristics, in a device.

Another issue is transistor variability. In simple terms, a given bulk CMOS transistor may perform differently from its nominal behavior in a device. This may produce random differences in terms of threshold voltages. The culprit is a phenomenon called random dopant fluctuation (RDF). RDF, according to experts, is caused by variations of the dopant atoms in the channel.

“We’ve been talking about RDF and halo designs since 65nm, and dealing with ever-degrading electrostatics,” said Terry Hook, a senior technical staff member at IBM Research. “28nm bulk poly SiON has very poor short-channel effects. And because of its relatively thick dielectric, it has relatively poor RDF, as well.”

To help solve the RDF and channel issues, chipmakers incorporated high-k/metal-gate technology to 28nm bulk CMOS. “The high-k version improves both of these,” he said. “And so, 28nm high-k is a very successful node.”

But even with high-k/metal-gate, issues remain with bulk CMOS. “In conventional transistors, the channel region below the gate is depleted of mobile charge, leaving the dopant atoms ionized,” he said. “The charge from those atoms, along with the gate work function, sets the threshold voltage. The depth of the depletion region controls the electrostatics. Below the depletion region is neutral silicon, with a lot of mobile carriers.”

There are several solutions on the table. One is a fully depleted transistor technology such as FD-SOI. Another is finFETs, which have the characteristics of fully depleted technology.

“For fully depleted SOI, the silicon is so thin that there is no neutral region,” Hook said. “The thickness of the depleted region, and hence the electrostatics, are determined not by the doping, but by the physical thickness. In fact, you can completely eliminate the doping and get essentially the same electrostatics. The absence of doping means better mobility and less variability.”

FinFETs also solve the problem, but the technology is expensive. “Bulk finFET does have a parasitic device below the surface that has to be shut off by doping,” Hook said. “So, there are definitely some drawbacks there.”

All told, FD-SOI addresses RDF and the short-channel effects. Back-biasing is another key selling point for FD-SOI. This feature enables IC designers to modulate transistor Vt, enabling them to tune the performance and power.

Despite its apparent advantages, FD-SOI has seen relatively limited adoption in the market over the years. Until recently, IBM and STMicroelectronics were among the few chipmakers that adopted FD-SOI. Intel, TSMC and others have never backed the technology.

There are two main reasons for this. First, SOI substrate costs are higher than bulk CMOS wafers. Second, the FD-SOI ecosystem, including EDA tools and IP, is lagging. “Bulk CMOS wafer prices are low, so it’s hard for FD-SOI to compete,” said Samuel Wang, an analyst at Gartner. “In addition, 28nm bulk has been around for many years. The skill set for designers has been well established.”

Over the last year, though, the FD-SOI camp has made progress on several fronts. For example, the customer base is growing, as NXP, Renesas, Sony and others have jumped on the FD-SOI bandwagon.

In addition, the FD-SOI foundries are expanding their efforts in the arena. Samsung, for example, is tweaking its 28nm strategy. Previously, the company offered both 28nm bulk and 28nm FD-SOI processes. Under the new strategy, Samsung will push 28nm FD-SOI for all new 28nm designs.

“We intend to focus all new engagements in design using 28nm FD-SOI,” Samsung’s Low said. “Of course, we still support the existing customers who are using 28nm bulk. That won’t change. But we think FD-SOI has enough benefits to attract new customers and designers.”

Last year, Samsung had one tape-out IC design for 28nm FD-SOI. Now, the company has 12 tape outs with several more in the pipeline, according to Low, who said FD-SOI is gaining traction in automotive, consumer, IoT and mobile. Samsung is also adding RF to the FD-SOI mix. “We are also going to add embedded nonvolatile features starting next year,” he said.

Meanwhile, GlobalFoundries is readying 22nm FD-SOI, a planar process said to provide finFET performance at 28nm costs. In addition, the company is also adding RF and more IPs to the technology.

So why should customers consider 22nm FD-SOI versus another process? It is low-power process that operates down to 0.4 volts, GlobalFoundries’ Kengeri said. “Cost and energy efficiency (are the key reasons),” he said.

But to gain more widespread adoption, FD-SOI still must address cost. “SOI wafers are obviously more expensive to produce than bulk wafers,” said David Fried, chief technology officer at Coventor. “But the price differential is pretty small relative to the total wafer processing cost. SOI process flows have some benefits in terms of process simplification, such as a shallower/simpler STI module. Often the process savings in a module like this can wash out the entire substrate cost differential. Wafer cost will also be dependent on volume. If FD-SOI succeeds in volume production, the wafer cost will be further reduced.”

Stay with bulk
Needless to say, the bulk CMOS camp isn’t throwing in the towel. TSMC, for example, recently rolled out 28ULP, a low-power 28nm technology. The process is a subset of its popular 28HPC+ technology.

“In addition, there will be more and more IPs developed for different flavors of 28nm,” Global Unichip’s Hwang said. “TSMC continues to improve the power consumption in bulk.”

For now, 28nm bulk CMOS will remain the dominate technology based on cost and other factors, according to Gartner’s Wang. “It seems that the number of FD-SOI tape outs has increased, but FD-SOI is still not gaining momentum,” Wang said.

So, which technology, bulk CMOS or FD-SOI, will prevail over the long run? Both technologies have their pluses and minuses, leaving foundry customers with some tough choices going forward.

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