category: Blogs – LPHP

category: Auto, Security & Edge AI

How Do We Push The Limits Of Power?
By Brian Fuller - 14 May, 2015 - Comments: 0

Just how far will we be able to push down power in electronics system design? A bit farther, according to experts presenting at the recent Electronic Design Processes Symposium in Monterey. A combination of materials, techniques, technology and cultural change will get the industry there. During a panel session comparing fully-depleted silicon-on-insulator (FD-SOI) with finFET technology, J... » read more

Microarchitecture Design For Low Power
By Anand Iyer - 14 May, 2015 - Comments: 0

As designs move to finFET process nodes, dynamic power reduction has become a requirement. Designers have to eliminate or minimize all sources of redundant switching activity in order to reduce dynamic power in the design. In our last blog, we looked at dynamic power wastage due to redundant adders and multipliers and how to gate these operators to save power. We also mentioned a couple of m... » read more

Correct-By-Design Methodology Requires Carefully Defined Constraints
By John McMillan - 14 May, 2015 - Comments: 0

Since the dawn of PCB usage, constraints have been an important part of the design. What are the dimensions? What weight of copper? Now, constraints have become much more than just physical dimensions. The most important constraints are defined by the design requirements of differential pairs, BGAs, low voltage devices, and high-speed parallel interfaces. The cost of rework skyrockets the fu... » read more

Power Reduction At RTL: Data Gating Adders And Multipliers
By Rob Eccles - 20 Apr, 2015 - Comments: 0

In our previous blog, “Low Power Paradox”, we discussed the implications of the move to FinFET technology. Dynamic power is dominant in finFET designs. Several techniques are available to reduce dynamic power consumption. Microarchitecture changes are one method and they can result in significant power savings. One technique that is frequently used is the data gating of adders and m... » read more

TSMC Tech Tour De Force
By Barry Pangrle - 13 Apr, 2015 - Comments: 0

TSMC held the first of its three North American Tech Symposiums on April 7 in San Jose, with the other two coming up in Boston on April 14 and in Austin on April 16. As was mentioned previously here, the record fast ramp-time of the 20nm node was highlighted among other technological achievements. TSMC also released its March revenue report on April 10, and it shows a dramatic 49.8% increase in... » read more

Taming Lint With Formal
By Ravindra Aneja - 09 Apr, 2015 - Comments: 1

Designers have been using Linting tools for many years to ensure designs adhere to recommended coding guidelines. Linting tools verify that RTL is written in an unambiguous way to ensure that downstream tools (simulation, synthesis, etc.) do not interpret the code incorrectly, resulting in design, verification, timing or implementation issues. Linting tools take advantage of fast and shallow... » read more

The Power Estimation Challenge
By Lauro Rizzatti - 09 Apr, 2015 - Comments: 0

If you wonder how important low power is in chip design today, consider the recent news in the blogosphere reporting the controversy surrounding Qualcomm’s Snapdragon 810 SoC — the company’s first flagship 64-bit chip, which will most likely power the top Android devices released in 2015. The story broke in early December along the lines that the 810 had problems with overheating. Whet... » read more

Fighting Dark Silicon With Specialized Hardware
By Ann Mutschler - 09 Apr, 2015 - Comments: 1

Looking at an SoC design from an architecture viewpoint, I’m hearing more discussion lately about the option of offloading tasks to specialized hardware. Especially where dark silicon is concerned, rather than having four or eight ARM processors — all with the same complexity — or cores like graphics processors, if you cannot use them all at full performance and they have to be shut o... » read more

UPF-Driven RTL Power Budgeting For Energy-Efficient Designs
By Arti Dwivedi - 09 Apr, 2015 - Comments: 1

Energy efficiency of devices has become more critical than ever, with shrinking geometries and increased performance requirements of SoCs in applications ranging from mobile, storage, automotive to processors. Power management, therefore, becomes an important part of IP and SoC design methodology. While power management is critical in all design stages, an important aspect of this methodolog... » read more

How We’ll Get There from Here
By Brian Fuller - 09 Apr, 2015 - Comments: 0

The electronics industry is like a battleship with remarkable handling properties. I thought about it this week sitting at an industry event a day after stumbling across Neptune—the technology project, not the god. Those two experiences forced me to rethink some fundamental assumptions about system design and how the ecosystem responds to change. If you’ve not heard of Neptune, it�... » read more

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