category: Low Power-High Performance

category: Auto, Security & Edge AI

Research Bits: Dec. 8
By Jesse Allen - 08 Dec, 2025 - Comments: 0

Iron-on circuit Researchers from Virginia Tech developed iron-on electronic circuits that can be applied to clothing. The patch uses electrically conductive liquid metal and a heat-activated adhesive to bond to fabric when heated with a hot iron. “E-textiles and wearable electronics can enable diverse applications from health care and environmental monitoring to robotics and human-machine... » read more

Research Bits: Dec. 2
By Jesse Allen - 02 Dec, 2025 - Comments: 0

Ionothermoelectric cooling Researchers from the University of Osaka, University of Tokyo, and Japan's National Institute of Advanced Industrial Science and Technology proposed an ionothermoelectric cooling strategy for chips that enhances cooling by driving the flow of ions through nanoscale channels. “We fabricated a nanosized pore in a semiconductor membrane and surrounded the nanopore ... » read more

Research Bits: Nov. 26
By Jesse Allen - 26 Nov, 2025 - Comments: 0

Hydrogel NAND gate Researchers from McMaster University and the University of Pittsburgh created a functionally complete NAND gate in a soft material using only beams of visible light. The NAND logic operation was completed by shining three self-trapped light beams into a photoresponsive merocyanine-functionalized hydrogel that is capable of performing compute tasks in the material itself w... » read more

Research Bits: Nov. 18
By Jesse Allen - 18 Nov, 2025 - Comments: 0

Rubbery CMOS Researchers at University of Illinois Urbana-Champaign, University of Houston, Ulsan National Institute of Science and Technology, Pusan National University, and Southeast University designed fully stretchable complementary integrated circuits composed of both elastic n-type and p-type transistors that provide the same functionality as conventional CMOS while retaining stable elec... » read more

Noise: A Chip Killer
By Brian Bailey - 13 Nov, 2025 - Comments: 0

Noise has always been important to communications experts, but it's quickly becoming an issue that every semiconductor designer has to contend with. Some chips already have been compromised. Noise can be defined as any deviation from the ideal that can impact intended functionality. When it comes to semiconductors, that could mean the ability to reliably extract a signal value at the intende... » read more

Opportunities And Challenges With Open-Source Hardware In System Development
By Roland Jancke - 13 Nov, 2025 - Comments: 0

For many years now, there has been a trend toward open source in the field of system development. It can be seen in software libraries for the product itself as well as in development tools. A clear motivation for open source lies in the fact that not charging license fees makes a product more attractive on the market. It may also enable further development of the software component, dependi... » read more

Scaling AI Infrastructure: The Critical Role Of PCIe 7.0 Retimers
By Lou Ternullo - 13 Nov, 2025 - Comments: 0

In a previous blog, Scaling in the AI Era: The Role of PCI Express 7.0 Switches in Next-Gen Data Centers, we explored how PCIe 7.0 switches enable high-bandwidth, low-latency interconnects for AI-driven data centers. Switches are essential for building flexible, composable architectures that connect thousands of GPUs, accelerators, and memory subsystems. But as AI clusters grow in size and comp... » read more

Power Integrity And Voltage Issues Get Harder To Detect And Solve
By Ann Mutschler - 13 Nov, 2025 - Comments: 0

Voltage and power integrity are becoming increasingly critical and challenging for chip designers and architects, regardless of which process technology they are using or which market they are targeting. An explosion of features vying unevenly for current is increasing the number of constraints and possible interactions that engineers need to sort through to ensure reliability. These include... » read more

Accellera Standard Supports Hierarchical Data Model For CDC And RDC Analysis
By Farhad Ahmed - 13 Nov, 2025 - Comments: 0

The hierarchical flow for clock domain crossing (CDC) and reset domain crossing (RDC) is a methodology used in the verification of large, complex digital integrated circuits. It's a divide-and-conquer approach that significantly improves the efficiency and turnaround time for ensuring design reliability against metastability and other issues at asynchronous boundaries. Questa CDC and RDC sol... » read more

Predictable Design Optimization And Closure With Adaptive Scenario Compression
By James Chuang - 13 Nov, 2025 - Comments: 0

Modern semiconductor chip design faces growing complexity due to numerous timing scenarios driven by varying operating conditions and physical effects. This complexity is especially pronounced in mobile and automotive chips, which require optimization across diverse performance and reliability demands. Designers currently focus on a limited subset of scenarios to manage computational load, but ... » read more

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