Accellera Standard Supports Hierarchical Data Model For CDC And RDC Analysis


The hierarchical flow for clock domain crossing (CDC) and reset domain crossing (RDC) is a methodology used in the verification of large, complex digital integrated circuits. It's a divide-and-conquer approach that significantly improves the efficiency and turnaround time for ensuring design reliability against metastability and other issues at asynchronous boundaries. Questa CDC and RDC sol... » read more

Predictable Design Optimization And Closure With Adaptive Scenario Compression


Modern semiconductor chip design faces growing complexity due to numerous timing scenarios driven by varying operating conditions and physical effects. This complexity is especially pronounced in mobile and automotive chips, which require optimization across diverse performance and reliability demands. Designers currently focus on a limited subset of scenarios to manage computational load, but ... » read more

Future Architecture Technologies: POE2 And vMTE


Future Architecture Technologies are features being developed for currently unreleased versions of the Arm architecture. Arm provides the ecosystem with relevant information and specifications in advance, ensuring software support for when new technologies are realized in hardware. This blog introduces two future technologies: Permission Overlay Extension version 2 (POE2), and Virtual T... » read more

Multiple AI Scale-Up Options Emerge


Artificial intelligence (AI) workloads are very different from those traditionally run inside of data centers, and while the current infrastructure can accommodate those needs, there is a constant demand for higher performance and better power efficiency. It can take months to train a large language model, even with a huge number of processing elements. Typically this involves commandeering ... » read more

PCIe Low-Power Validation Challenges And Potential Solutions


As chip complexities increase and the industry evolves to more battery-powered devices, power-aware/consumption research becomes an integral part of design in the industry. Low power is crucial in ASIC applications to ensure longevity, durability, and reliability. PCI-SIG has focused on reducing power consumption while the PCIe interface is active to enable better platform power management (... » read more

The Future Of Digital Engineering In The Age Of AI


Digital engineering gives innovators creative agency to test the limits of their ideas in a virtual environment. It is in this convergence of digital technologies, data-driven models, and advanced simulations where new designs are born at unprecedented levels of speed and accuracy. Adding artificial intelligence (AI) into the mix further accelerates innovation by unlocking opportunities to a... » read more

High Bandwidth Memory (HBM): Everything You Need To Know


In an era where data-intensive applications, from AI and machine learning to high-performance computing (HPC) and gaming, are pushing the limits of traditional memory architectures, High Bandwidth Memory (HBM) has emerged as a high-performance, power-efficient solution. As industries demand faster, higher throughput processing, understanding HBM’s architecture, benefits, and evolving role in ... » read more

Standardization Of HDMs For Hierarchical CDC And RDC Analysis


Currently hierarchical data models (HDM) must be generated with the same EDA tool that customers will use to consume the HDM for CDC and RDC analysis at the SoC level. To resolve this problem a CDC Working Group was created within the Accellera organization. The goal of this Working Group is to create a standard format for HDMs so the models can be consumed by any EDA tool irrespective of the s... » read more

A Guide To Accelerating Your Design Timeline With Electromagnetic Analysis


Today’s high-speed PCB and system-level design demands fast, accurate simulation. This ebook explains how to choose the right electromagnetic (EM) solver—from 2D and hybrid methods to full 3D FEM—for every stage of the design process. Inside, you’ll learn: When to use 2D, 3D planar (hybrid), or full-wave 3D solvers How the cloud-native parallelized Cadence Clarity 3D Tran... » read more

Why Arm For Cloud: At A Glance


This report explores the performance and cost-efficiency benefits of Arm processors on AWS, specifically examining Arm Neoverse-powered AWS Graviton4 processors in comparison to the latest available generation AMD and Intel based AWS EC2 alternatives. As detailed in this Lab Insight Report, Signal65 conducted hands on performance testing and cost efficiency analysis across four distinct workloa... » read more

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