Achieving Reliable 2m+ DAC Connectivity For AI Scale Networks With 224G PHY IP


As artificial intelligence workloads and hyperscale data centers continue to evolve, the requirements for networking infrastructure are becoming increasingly stringent. High-speed, reliable connectivity is essential to support the massive data flow and low-latency demands of AI-scale environments. Passive direct attach copper (DACs) remains an attractive choice for hyperscalers and system vendo... » read more

Data Centers Boost Voltage For Higher Efficiency


The power architecture used in HPC and AI data centers today is about to undergo a significant change in an effort to boost power efficiency. While voltages at the chip level will remain the same, the voltages leading to those chips will be kept higher for longer distances. This change has broad implications for DC-DC converters. The existing architecture brings AC to each rack, converts it ... » read more

GDDR7 Tackles Massive-Context AI Inference


The AI hardware landscape is evolving at breakneck speed, and memory technology is at the heart of this transformation. NVIDIA’s recent announcement of Rubin CPX, a new class of GPU purpose-built for massive-context inference, underscores this trend. Rubin CPX is designed to tackle workloads that require reasoning across millions of tokens. Use cases include long-form generative video, comple... » read more

Overflowing Zoo: The Power Of Compilers


The term “model zoo” first gained prominence in the world of Artificial Intelligence/Machine Learning (AI/ML) beginning in the 2016-2017 timeframe. Originally used to describe open-source public repositories of working AI models — the most prominent of which today is Hugging Face — the term has since been adopted by nearly all vendors of AI chips and licensable Neural Processors Units (... » read more

Startup Tips To Get From Seed Funding To Series A, B, C


Startups are often created by experienced engineers who figure out how to solve a technical problem they are dealing with at work, or by PhD candidates in research labs before they have even started their first full-time job. Either way, getting seed money to the tune of a few million dollars is relatively easy compared to securing further rounds of funding and achieving the company’s exit go... » read more

Developing Next-Generation Integrated Optical Engines


By Susan Coleman and Emily Gerken Data demand is soaring worldwide as high-resolution video streaming, virtual reality, the Internet of Things (IoT), high-performance computing (HPC), and artificial intelligence and machine learning (AI/ML) drive an insatiable appetite for data. As a result, networks and data centers face increasing pressure to expand bandwidth, reduce latency, and lower pow... » read more

Current Problems Grow For Power Delivery


IR drop is becoming more problematic for a growing proportion of designs, an indication that the power delivery network (PDN) is not providing enough current to parts of the design when required. Unfortunately, there is no easy fix to this problem. In the past, when voltages were much higher, a small voltage droop didn't really matter. At the same time, wires were much thicker and presented ... » read more

EBook: Helping To Realize Chiplet Ambitions


The future of physical AI, from autonomous vehicles to robotics and aerospace, depends on overcoming the limitations of monolithic SoCs. As computing demands grow, a shift to scalable, modular, and reusable chiplet-based architectures is essential. This transition presents new challenges, from ensuring interoperability to managing complex system-level integration. How can you navigate this land... » read more

ONNX And Python To C++: State-Of-The-Art Graph Compilation


Nigel Drego, Co-founder and Chief Technology Officer at Quadric, presented the “ONNX and Python to C++: State-of-the-art Graph Compilation” tutorial at this year's Embedded Vision Summit. Quadric’s Chimera general-purpose neural processor executes complete AI/ML graphs—all layers, including pre- and post-processing functions traditionally run on separate DSP processors. Read more here. » read more

Frequency-Impedence Verification Of Power Delivery Network With HyperLynx PI For AMD Versal Adaptive SoC Devices


HyperLynx Decoupling analysis and the PDN Decoupling Optimizer are powerful tools for exploring various PDN structures and decoupling strategies. This paper presents a study showcasing the advantages of performing a HyperLynx decoupling analysis to verify PDN performance, and it highlights the extensive collaboration between Siemens and AMD in creating a complete system design flow for performi... » read more

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